From: Andrew Lunn <andrew@lunn.ch>
To: lizhi2@eswincomputing.com
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com,
rmk+kernel@armlinux.org.uk, maxime.chevallier@bootlin.com,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, ningyu@eswincomputing.com,
linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com,
pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com
Subject: Re: [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description
Date: Thu, 7 May 2026 14:29:10 +0200 [thread overview]
Message-ID: <2436c6e9-4aad-4ffd-9fef-0cbbe38dc66d@lunn.ch> (raw)
In-Reply-To: <20260507083136.175-1-lizhi2@eswincomputing.com>
> ethernet@50400000 {
> compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
> reg = <0x50400000 0x10000>;
> - clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
> - <&d0_clock 193>;
> - clock-names = "axi", "cfg", "stmmaceth", "tx";
> interrupt-parent = <&plic>;
> interrupts = <61>;
> interrupt-names = "macirq";
> - phy-mode = "rgmii-id";
> - phy-handle = <&phy0>;
> + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
> + <&d0_clock 193>;
> + clock-names = "axi", "cfg", "stmmaceth", "tx";
Please don't move the clocks around, since they have nothing to do
with RGMII delays.
> resets = <&reset 95>;
> reset-names = "stmmaceth";
> - rx-internal-delay-ps = <200>;
> - tx-internal-delay-ps = <200>;
> - eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
> - snps,axi-config = <&stmmac_axi_setup>;
> + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> snps,aal;
> snps,fixed-burst;
> snps,tso;
> - stmmac_axi_setup: stmmac-axi-config {
> + snps,axi-config = <&stmmac_axi_setup_gmac0>;
> +
> + stmmac_axi_setup_gmac0: stmmac-axi-config {
And what do these changes have to do with RGMII delays?
Andrew
---
pw-bot: cr
next prev parent reply other threads:[~2026-05-07 12:29 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 8:30 [PATCH net v1 0/2] net: stmmac: eic7700: fix delay calculation and initialization ordering lizhi2
2026-05-07 8:31 ` [PATCH net v1 1/2] dt-bindings: ethernet: eswin: refine delay model and HSP register description lizhi2
2026-05-07 12:29 ` Andrew Lunn [this message]
2026-05-08 5:47 ` 李志
2026-05-07 17:24 ` Conor Dooley
2026-05-08 5:43 ` 李志
2026-05-08 14:55 ` Conor Dooley
2026-05-07 8:32 ` [PATCH net v1 2/2] net: stmmac: eic7700: fix delay step calculation and ensure safe register initialization lizhi2
2026-05-07 11:21 ` Maxime Chevallier
2026-05-08 6:25 ` 李志
2026-05-08 17:14 ` sashiko-bot
2026-05-09 5:28 ` 李志
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