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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Content-Language: en-US To: Eric Lin , conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, maz@kernel.org, chenhuacai@kernel.org, baolu.lu@linux.intel.com, will@kernel.org, kan.liang@linux.intel.com, nnac123@linux.ibm.com, pierre.gondois@arm.com, huangguangbin2@huawei.com, jgross@suse.com, chao.gao@intel.com, maobibo@loongson.cn, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dslin1010@gmail.com Cc: Zong Li , Nick Hu References: <20230616063210.19063-1-eric.lin@sifive.com> <20230616063210.19063-4-eric.lin@sifive.com> From: Krzysztof Kozlowski In-Reply-To: <20230616063210.19063-4-eric.lin@sifive.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 16/06/2023 08:32, Eric Lin wrote: > This add YAML DT binding documentation for SiFive Private L2 > cache controller > > Signed-off-by: Eric Lin > Reviewed-by: Zong Li > Reviewed-by: Nick Hu > --- > .../bindings/riscv/sifive,pL2Cache0.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml > new file mode 100644 > index 000000000000..b5d8d4a39dde > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive,pL2Cache0.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +# Copyright (C) 2023 SiFive, Inc. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/sifive,pL2Cache0.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Private L2 Cache Controller > + > +maintainers: > + - Greentime Hu > + - Eric Lin > + > +description: > + The SiFive Private L2 Cache Controller is per hart and communicates with both the upstream > + L1 caches and downstream L3 cache or memory, enabling a high-performance cache subsystem. > + All the properties in ePAPR/DeviceTree specification applies for this platform. Drop the last sentence. Why specification would not apply? > + > +allOf: > + - $ref: /schemas/cache-controller.yaml# > + > +select: > + properties: > + compatible: > + contains: > + enum: > + - sifive,pL2Cache0 > + - sifive,pL2Cache > + > + required: > + - compatible > + > +properties: > + compatible: > + items: You have only one item, so no need for items... unless you just missed proper fallback. > + - enum: > + - sifive,pL2Cache0 > + - sifive,pL2Cache1 What is "0" and "1" here? What do these compatibles represent? Why they do not have any SoC related part? > + > + cache-block-size: > + const: 64 > + > + cache-level: > + const: 2 > + > + cache-sets: > + const: 512 > + > + cache-size: > + const: 262144 Are you sure? So all private L2 cache controllers will have fixed size of cache? > + > + cache-unified: true > + > + reg: > + maxItems: 1 > + > + next-level-cache: true > + > +additionalProperties: false > + > +required: required: goes before additionalProperties:. Best regards, Krzysztof