From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 003FBC6FA82 for ; Fri, 23 Sep 2022 13:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229949AbiIWNdb (ORCPT ); Fri, 23 Sep 2022 09:33:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbiIWNda (ORCPT ); Fri, 23 Sep 2022 09:33:30 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8688A131F54 for ; Fri, 23 Sep 2022 06:33:27 -0700 (PDT) Received: from p508fdb48.dip0.t-ipconnect.de ([80.143.219.72] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1obinv-00074F-K3; Fri, 23 Sep 2022 15:33:19 +0200 From: Heiko Stuebner To: Rob Herring , Krzysztof Kozlowski , Kever Yang , Jagan Teki Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki , Jon Lin , Sugar Zhang Subject: Re: [PATCH v5 6/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Date: Fri, 23 Sep 2022 15:33:18 +0200 Message-ID: <2439124.NgBsaNRSFp@phil> In-Reply-To: <20220915163947.1922183-7-jagan@edgeble.ai> References: <20220915163947.1922183-1-jagan@edgeble.ai> <20220915163947.1922183-7-jagan@edgeble.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Am Donnerstag, 15. September 2022, 18:39:47 CEST schrieb Jagan Teki: > RV1126 is a high-performance vision processor SoC for IPC/CVR, > especially for AI related application. > > It is based on quad-core ARM Cortex-A7 32-bit core which integrates > NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core > and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 > hybrid operation and computing power is up to 2.0TOPs. > > This patch add basic core dtsi support. > > Signed-off-by: Jon Lin > Signed-off-by: Sugar Zhang > Signed-off-by: Jagan Teki hmm, this series doesn't really provide any board for the rv1126, so we essentially don't even get any compile-time tests, as nothing is using this dtsi. Can we please change that? Thanks Heiko