* [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform
@ 2025-10-17 14:16 Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
` (9 more replies)
0 siblings, 10 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia, Bryan O'Donoghue
Qualcomm kaanapali platform have a newer generation of video IP, iris4
or vpu4. The hardware have evolved mostly w.r.t higher number of power
domains as well as multiple clock sources. It has support for new
codec(apv), when compared to prior generation.
The series describes the binding interfaces of the hardware, buffer
calculation and power sequence for vpu4, and add the platform data at
the end.
Please review and share your comments.
Following are the compliance and functional validation reports
v4l2-compliance report, for decoder followed by encoder, including
streaming tests:
v4l2-compliance 1.31.0-5396, 64 bits, 64-bit time_t
v4l2-compliance SHA: 3f22c6fcee75 2025-09-18 09:49:23
Compliance test for iris_driver device /dev/video0:
Driver Info:
Driver name : iris_driver
Card type : Iris Decoder
Bus info : platform:2000000.video-codec
Driver version : 6.17.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected Stateful Decoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 10 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test CREATE_BUFS maximum buffers: OK
test VIDIOC_REMOVE_BUFS: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
[ 328.905995] qcom-iris 2000000.video-codec: invalid plane
[ 332.917543] qcom-iris 2000000.video-codec: invalid plane
test blocking wait: OK
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
Video Capture Multiplanar: Captured 21481 buffers
[ 350.438406] qcom-iris 2000000.video-codec: invalid plane
[ 350.447079] qcom-iris 2000000.video-codec: invalid plane
[ 350.458821] qcom-iris 2000000.video-codec: invalid plane
[ 350.465860] qcom-iris 2000000.video-codec: invalid plane
test MMAP (select, REQBUFS): OK
Video Capture Multiplanar: Captured 21481 buffers
[ 363.878157] qcom-iris 2000000.video-codec: invalid plane
[ 363.886546] qcom-iris 2000000.video-codec: invalid plane
[ 363.898475] qcom-iris 2000000.video-codec: invalid plane
[ 363.905527] qcom-iris 2000000.video-codec: invalid plane
test MMAP (epoll, REQBUFS): OK
Video Capture Multiplanar: Captured 21481 buffers
[ 377.209312] qcom-iris 2000000.video-codec: invalid plane
[ 377.218027] qcom-iris 2000000.video-codec: invalid plane
[ 377.233635] qcom-iris 2000000.video-codec: invalid plane
[ 377.241360] qcom-iris 2000000.video-codec: invalid plane
test MMAP (select, CREATE_BUFS): OK
Video Capture Multiplanar: Captured 21481 buffers
[ 390.624700] qcom-iris 2000000.video-codec: invalid plane
[ 390.633590] qcom-iris 2000000.video-codec: invalid plane
[ 390.645629] qcom-iris 2000000.video-codec: invalid plane
[ 390.652618] qcom-iris 2000000.video-codec: invalid plane
test MMAP (epoll, CREATE_BUFS): OK
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for iris_driver device /dev/video0: 54, Succeeded: 54, Failed: 0,
Warnings: 0
Compliance test for iris_driver device /dev/video1:
Driver Info:
Driver name : iris_driver
Card type : Iris Encoder
Bus info : platform:2000000.video-codec
Driver version : 6.17.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected Stateful Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 38 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test CREATE_BUFS maximum buffers: OK
test VIDIOC_REMOVE_BUFS: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
test blocking wait: OK
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
Video Capture Multiplanar: Captured 61 buffers
test MMAP (select, REQBUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (epoll, REQBUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (select, CREATE_BUFS): OK
Video Capture Multiplanar: Captured 61 buffers
test MMAP (epoll, CREATE_BUFS): OK
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for iris_driver device /dev/video1: 54, Succeeded: 54, Failed: 0,
Warnings: 0
gstreamer test:
Decoders validated with below commands, codec specific:
gst-launch-1.0 multifilesrc location=<input_file.h264> stop-index=0 !
parsebin ! v4l2h264dec ! video/x-raw ! videoconvert dither=none !
video/x-raw,format=I420 ! filesink location=<output_file.yuv>
gst-launch-1.0 multifilesrc location=<input_file.hevc> stop-index=0 !
parsebin ! v4l2h265dec ! video/x-raw ! videoconvert dither=none !
video/x-raw,format=I420 ! filesink location=<output_file.yuv>
gst-launch-1.0 filesrc location=<input_file.webm> stop-index=0 !
parsebin ! vp9dec ! video/x-raw ! videoconvert dither=none !
video/x-raw,format=I420 ! filesink location=<output_file.yuv>
Encoders validated with below commands:
gst-launch-1.0 -v filesrc location=<input_file.yuv> ! rawvideoparse
format=nv12 width=<width> height=<height> framerate=30/1 ! v4l2h264enc
capture-io-mode=4 output-io-mode=4 ! filesink sync=true
location=<output_file.h264>
gst-launch-1.0 -v filesrc location=<input_file.yuv> ! rawvideoparse
format=nv12 width=<width> height=<height> framerate=30/1 ! v4l2h265enc
capture-io-mode=4 output-io-mode=4 ! filesink sync=true
location=<output_file.hevc>
ffmpeg test:
Decoders validated with below commands:
ffmpeg -vcodec h264_v4l2m2m -i <input_file.h264> -pix_fmt nv12 -vsync 0
output_file.yuv -y
ffmpeg -vcodec hevc_v4l2m2m -i <input_file.hevc> -pix_fmt nv12 -vsync 0
output_file.yuv -y
ffmpeg -vcodec vp9_v4l2m2m -i <input_file.webm> -pix_fmt nv12 -vsync 0
output_file.yuv -y
v4l2-ctl test
Decoders validated with below commands:
v4l2-ctl --verbose --set-fmt-video-out=pixelformat=H264
--set-fmt-video=pixelformat=NV12 --stream-mmap --stream-out-mmap
--stream-from=<input_file.h264> --stream-to=<output_file.yuv>
v4l2-ctl --verbose --set-fmt-video-out=pixelformat=HEVC
--set-fmt-video=pixelformat=NV12 --stream-mmap --stream-out-mmap
--stream-from=input_file.bit --stream-to=<output_file.yuv>
v4l2-ctl --verbose --set-fmt-video-out=pixelformat=VP90
--set-fmt-video=pixelformat=NV12 --stream-mmap --stream-out-mmap
--stream-from-hdr=input_file.hdr --stream-mmap
--stream-to=<output_file.yuv>
Encoders validated with below commands:
v4l2-ctl --verbose
--set-fmt-video-out=width=<width>,height=<height>,pixelformat=NV12
--set-selection-output
target=crop,top=0,left=0,width=<width>,height=<height>
--set-fmt-video=pixelformat=H264 --stream-mmap --stream-out-mmap
--stream-from=<input_file.yuv> --stream-to=<output_file.h264> -d
/dev/video1
v4l2-ctl --verbose
--set-fmt-video-out=width=<width>,height=<height>,pixelformat=NV12
--set-selection-output
target=crop,top=0,left=0,width=<width>,height=<height>
--set-fmt-video=pixelformat=HEVC --stream-mmap --stream-out-mmap
--stream-from=<input_file.yuv> --stream-to=<output_file.hevc> -d
/dev/video1
Note: there is a crash observed while performing below sequence
rmmod qcom-iris
modprobe qcom-iris
The crash is not seen if ".skip_retention_level = true" is added to
mmcx and mmcx_ao power domains in rpmhpd.c. This is under debug with
rpmh module owner to conclude if it to be fixed differently.
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
Changes in v2:
- Dropped dependencies from binding (Dmitry).
- Dropped optional items from binding (Dmitry, Krzysztof, Konrad).
- Updated binding in sorted order and proper alignment (Krzysztof).
- Fixed order of newly introduced kaanapali struct (Dmitry, Bryan)
- Improved readability of buffer size calculation (Bryan)
- Optimized fuse register read (Konrad).
- Fixed order of vpu register defines (Dmitry).
- Addressed few other log and commit related comments (Bryan)
- Link to v1: https://lore.kernel.org/r/20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com
---
Vikash Garodia (8):
media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
media: iris: Add support for multiple clock sources
media: iris: Add support for multiple TZ content protection(CP) configs
media: iris: Introduce buffer size calculations for vpu4
media: iris: Move vpu register defines to common header file
media: iris: Move vpu35 specific api to common to use for vpu4
media: iris: Introduce vpu ops for vpu4 with necessary hooks
media: iris: Add platform data for kaanapali
.../bindings/media/qcom,kaanapali-iris.yaml | 231 +++++++++++++
drivers/media/platform/qcom/iris/Makefile | 1 +
drivers/media/platform/qcom/iris/iris_firmware.c | 23 +-
.../platform/qcom/iris/iris_platform_common.h | 12 +-
.../media/platform/qcom/iris/iris_platform_gen2.c | 119 ++++++-
.../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++
.../platform/qcom/iris/iris_platform_sm8250.c | 21 +-
drivers/media/platform/qcom/iris/iris_power.c | 2 +-
drivers/media/platform/qcom/iris/iris_probe.c | 24 +-
drivers/media/platform/qcom/iris/iris_resources.c | 16 +-
drivers/media/platform/qcom/iris/iris_resources.h | 1 +
drivers/media/platform/qcom/iris/iris_vpu3x.c | 195 +----------
drivers/media/platform/qcom/iris/iris_vpu4x.c | 358 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 345 ++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 15 +
drivers/media/platform/qcom/iris/iris_vpu_common.c | 168 ++++++++--
drivers/media/platform/qcom/iris/iris_vpu_common.h | 5 +
.../platform/qcom/iris/iris_vpu_register_defines.h | 32 ++
18 files changed, 1377 insertions(+), 254 deletions(-)
---
base-commit: f215d17ddbe8502804ae65d8f855100daf347061
change-id: 20250924-knp_video-aaf4c40be747
Best regards,
--
Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-18 15:58 ` Krzysztof Kozlowski
2025-10-17 14:16 ` [PATCH v2 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
` (8 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Kaanapali SOC brings in the new generation of video IP i.e iris4. When
compared to previous generation, iris3x, it has,
- separate power domains for stream and pixel processing hardware blocks
(bse and vpp).
- additional power domain for apv codec.
- power domains for individual pipes (VPPx).
- different clocks and reset lines.
Iommus include all the different stream-ids which can be possibly
generated by vpu4 video hardware in both secure and non secure execution
mode.
The vpu have reserved iova, i.e some portion of the addressable range is
reserved for IO registers. Iris_resv would describe the acceptable
address range.
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../bindings/media/qcom,kaanapali-iris.yaml | 231 +++++++++++++++++++++
1 file changed, 231 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..39e9ac9dad2212e5ae8dc3d45e764418fe7d358d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
@@ -0,0 +1,231 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Iris video encoder and decoder
+
+maintainers:
+ - Vikash Garodia <vikash.garodia@oss.qualcomm.com>
+ - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
+
+description:
+ The iris video processing unit is a video encode and decode accelerator
+ present on Qualcomm Kaanapali SoC.
+
+properties:
+ compatible:
+ const: qcom,kaanapali-iris
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec_bse
+ - const: vcodec_vpp0
+ - const: vcodec_vpp1
+ - const: vcodec_apv
+
+ dma-coherent: true
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 3
+ maxItems: 8
+
+ memory-region:
+ minItems: 1
+ maxItems: 2
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ power-domains:
+ maxItems: 7
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vpp0
+ - const: vpp1
+ - const: apv
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core_freerun_reset
+ - const: vcodec0_core_freerun_reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - iommus
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@2000000 {
+ compatible = "qcom,kaanapali-iris";
+ reg = <0x02000000 0xf0000>;
+
+ clocks = <&gcc_video_axi0_clk>,
+ <&video_cc_mvs0c_clk>,
+ <&video_cc_mvs0_clk>,
+ <&gcc_video_axi1_clk>,
+ <&video_cc_mvs0c_freerun_clk>,
+ <&video_cc_mvs0_freerun_clk>,
+ <&video_cc_mvs0b_clk>,
+ <&video_cc_mvs0_vpp0_clk>,
+ <&video_cc_mvs0_vpp1_clk>,
+ <&video_cc_mvs0a_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec_bse",
+ "vcodec_vpp0",
+ "vcodec_vpp1",
+ "vcodec_apv";
+
+ dma-coherent;
+
+ interconnects = <&gem_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video_mvp &mc_virt_slave_ebi1>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x1a20 0x0>,
+ <&apps_smmu 0x1943 0x0>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ memory-region = <&video_mem>, <&iris_resv>;
+
+ power-domains = <&video_cc_mvs0c_gdsc>,
+ <&video_cc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&video_cc_mvs0_vpp0_gdsc>,
+ <&video_cc_mvs0_vpp1_gdsc>,
+ <&video_cc_mvs0a_gdsc>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0",
+ "vpp1",
+ "apv";
+
+ resets = <&gcc_video_axi0_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
+ <&video_cc_mvs0c_freerun_clk_ares>,
+ <&video_cc_mvs0_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>,
+ <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l0>,
+ <&rpmhpd_opp_turbo_l0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 2/8] media: iris: Add support for multiple clock sources
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:06 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs Vikash Garodia
` (7 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
vpu4 depends on more than one clock source. Thus far hardware versions
up to vpu3x have been clocked by a single source.
This adds support for multiple clocks by,
- Adding a lookup table
- Configuring OPP table for video device with different video clocks
- Setting OPP for multiple clocks during dev_pm_opp_set_opp()
This patch extends the support for multiple clocks in driver, which
would be used in subsequent patch for kaanapali, when the platform data
is prepared.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../media/platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++
.../media/platform/qcom/iris/iris_platform_sm8250.c | 6 ++++++
drivers/media/platform/qcom/iris/iris_power.c | 2 +-
drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++------------
drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++--
drivers/media/platform/qcom/iris/iris_resources.h | 1 +
drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
8 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 58d05e0a112eed25faea027a34c719c89d6c3897..df03de08c44839c1b6c137874eb7273c638d5f2c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -206,6 +206,7 @@ struct iris_platform_data {
const char * const *opp_pd_tbl;
unsigned int opp_pd_tbl_size;
const struct platform_clk_data *clk_tbl;
+ const char * const *opp_clk_tbl;
unsigned int clk_tbl_size;
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 36d69cc73986b74534a2912524c8553970fd862e..fea800811a389a58388175c733ad31c4d9c636b0 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -633,6 +633,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8550_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct ubwc_config_data ubwc_config_sm8550 = {
.max_channels = 8,
.mal_length = 32,
@@ -756,6 +761,7 @@ struct iris_platform_data sm8550_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
@@ -848,6 +854,7 @@ struct iris_platform_data sm8650_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu33_p4.mbn",
@@ -930,6 +937,7 @@ struct iris_platform_data sm8750_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8750_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu35_p4.mbn",
@@ -1017,6 +1025,7 @@ struct iris_platform_data qcs8300_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 16486284f8acccf6a95a27f6003e885226e28f4d..1b1b6aa751106ee0b0bc71bb0df2e78340190e66 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8250_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct tz_cp_config tz_cp_config_sm8250 = {
.cp_start = 0,
.cp_size = 0x25800000,
@@ -333,6 +338,7 @@ struct iris_platform_data sm8250_data = {
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
+ .opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu-1.0/venus.mbn",
diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c
index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03e5e49b9a2bd5c 100644
--- a/drivers/media/platform/qcom/iris/iris_power.c
+++ b/drivers/media/platform/qcom/iris/iris_power.c
@@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
}
core->power.clk_freq = freq;
- ret = dev_pm_opp_set_rate(core->dev, freq);
+ ret = iris_opp_set_rate(core->dev, freq);
mutex_unlock(&core->lock);
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 00e99be16e087c4098f930151fd76cd381d721ce..ad82a62f8b923d818ffe77c131d7eb6da8c34002 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
static int iris_init_power_domains(struct iris_core *core)
{
- const struct platform_clk_data *clk_tbl;
- u32 clk_cnt, i;
int ret;
struct dev_pm_domain_attach_data iris_pd_data = {
@@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
.pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
};
+ struct dev_pm_opp_config iris_opp_clk_data = {
+ .clk_names = core->iris_platform_data->opp_clk_tbl,
+ .config_clks = dev_pm_opp_config_clks_simple,
+ };
+
ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
if (ret < 0)
return ret;
@@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
if (ret < 0)
return ret;
- clk_tbl = core->iris_platform_data->clk_tbl;
- clk_cnt = core->iris_platform_data->clk_tbl_size;
-
- for (i = 0; i < clk_cnt; i++) {
- if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
- ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
- if (ret)
- return ret;
- }
- }
+ ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
+ if (ret)
+ return ret;
return devm_pm_opp_of_add_table(core->dev);
}
diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index cf32f268b703c1c042a9bcf146e444fff4f4990d..939f6617f2631503fa8cb3e874b9de6b2fbe7b76 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -4,6 +4,7 @@
*/
#include <linux/clk.h>
+#include <linux/devfreq.h>
#include <linux/interconnect.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
@@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
+int iris_opp_set_rate(struct device *dev, unsigned long freq)
+{
+ struct dev_pm_opp *opp __free(put_opp);
+
+ opp = devfreq_recommended_opp(dev, &freq, 0);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ return dev_pm_opp_set_opp(dev, opp);
+}
+
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
+ ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
@@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, 0);
+ ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e048285f82446c6 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.h
+++ b/drivers/media/platform/qcom/iris/iris_resources.h
@@ -8,6 +8,7 @@
struct iris_core;
+int iris_opp_set_rate(struct device *dev, unsigned long freq);
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_unset_icc_bw(struct iris_core *core);
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..bbd999a41236dca5cf5700e452a6fed69f4fc922 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -266,7 +266,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
void iris_vpu_power_off(struct iris_core *core)
{
- dev_pm_opp_set_rate(core->dev, 0);
+ iris_opp_set_rate(core->dev, 0);
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
iris_unset_icc_bw(core);
@@ -352,7 +352,7 @@ int iris_vpu_power_on(struct iris_core *core)
freq = core->power.clk_freq ? core->power.clk_freq :
(u32)ULONG_MAX;
- dev_pm_opp_set_rate(core->dev, freq);
+ iris_opp_set_rate(core->dev, freq);
core->iris_platform_data->set_preset_registers(core);
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:35 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
` (6 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia, Bryan O'Donoghue
vpu4 needs an additional configuration with respect to CP regions. Make
the CP configuration as array such that the multiple configuration can be
managed per platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_firmware.c | 23 ++++++++++++---------
.../platform/qcom/iris/iris_platform_common.h | 3 ++-
.../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++++++++++--------
.../platform/qcom/iris/iris_platform_sm8250.c | 15 ++++++++------
4 files changed, 39 insertions(+), 26 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
index 9ab499fad946446a87036720f49c9c8d311f3060..9186e0144dc0df4045c9995adc5fc93993cc3fba 100644
--- a/drivers/media/platform/qcom/iris/iris_firmware.c
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -70,9 +70,9 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
int iris_fw_load(struct iris_core *core)
{
- struct tz_cp_config *cp_config = core->iris_platform_data->tz_cp_config_data;
+ const struct tz_cp_config *cp_config;
const char *fwpath = NULL;
- int ret;
+ int i, ret;
ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0,
&fwpath);
@@ -91,14 +91,17 @@ int iris_fw_load(struct iris_core *core)
return ret;
}
- ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
- cp_config->cp_size,
- cp_config->cp_nonpixel_start,
- cp_config->cp_nonpixel_size);
- if (ret) {
- dev_err(core->dev, "protect memory failed\n");
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
- return ret;
+ for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
+ cp_config = &core->iris_platform_data->tz_cp_config_data[i];
+ ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
+ cp_config->cp_size,
+ cp_config->cp_nonpixel_start,
+ cp_config->cp_nonpixel_size);
+ if (ret) {
+ dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
+ qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ return ret;
+ }
}
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index df03de08c44839c1b6c137874eb7273c638d5f2c..ae49e95ba2252fc1442f7c81d8010dbfd86da0da 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -220,7 +220,8 @@ struct iris_platform_data {
u32 inst_fw_caps_dec_size;
struct platform_inst_fw_cap *inst_fw_caps_enc;
u32 inst_fw_caps_enc_size;
- struct tz_cp_config *tz_cp_config_data;
+ const struct tz_cp_config *tz_cp_config_data;
+ u32 tz_cp_config_data_size;
u32 core_arch;
u32 hw_response_timeout;
struct ubwc_config_data *ubwc_config;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index fea800811a389a58388175c733ad31c4d9c636b0..00c6b9021b98aac80612b1bb9734c8dac8146bd9 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -648,11 +648,13 @@ static struct ubwc_config_data ubwc_config_sm8550 = {
.bank_spreading = 1,
};
-static struct tz_cp_config tz_cp_config_sm8550 = {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
+static const struct tz_cp_config tz_cp_config_sm8550[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
};
static const u32 sm8550_vdec_input_config_params_default[] = {
@@ -771,7 +773,8 @@ struct iris_platform_data sm8550_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -864,7 +867,8 @@ struct iris_platform_data sm8650_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -947,7 +951,8 @@ struct iris_platform_data sm8750_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
@@ -1035,7 +1040,8 @@ struct iris_platform_data qcs8300_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
- .tz_cp_config_data = &tz_cp_config_sm8550,
+ .tz_cp_config_data = tz_cp_config_sm8550,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
.core_arch = VIDEO_ARCH_LX,
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.ubwc_config = &ubwc_config_sm8550,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 1b1b6aa751106ee0b0bc71bb0df2e78340190e66..8927c3ff59dab59c7d2cbcd92550f9ee3a2b5c1e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[] = {
NULL,
};
-static struct tz_cp_config tz_cp_config_sm8250 = {
- .cp_start = 0,
- .cp_size = 0x25800000,
- .cp_nonpixel_start = 0x01000000,
- .cp_nonpixel_size = 0x24800000,
+static const struct tz_cp_config tz_cp_config_sm8250[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
};
static const u32 sm8250_vdec_input_config_param_default[] = {
@@ -348,7 +350,8 @@ struct iris_platform_data sm8250_data = {
.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
- .tz_cp_config_data = &tz_cp_config_sm8250,
+ .tz_cp_config_data = tz_cp_config_sm8250,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
.num_vpp_pipe = 4,
.max_session_count = 16,
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (2 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:25 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
` (5 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Introduces vp4 buffer size calculation for both encoder and decoder.
Reuse the buffer size calculation which are common, while adding the
vpu4 ones separately.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 345 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 15 +
2 files changed, 360 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..8cc52d7aba3ffb968191519c1a1a10e326403205 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -1408,6 +1408,307 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
}
+static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
+{
+ u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
+ u32 dpb_opb = 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT);
+ u32 num_luma_chrome_plane = 2;
+
+ return dpb_opb = num_luma_chrome_plane * ALIGN(dpb_opb, DMA_ALIGNMENT);
+}
+
+static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp, num_lcu_per_pipe;
+ u32 lcu_size = 64, fe_top_ctrl_line_numbers = 3, fe_top_data_luma_line_numbers = 2,
+ fe_top_data_chroma_line_numbers = 3, fe_lft_ctrl_line_numbers = 4,
+ fe_lft_db_data_line_numbers = 2, fe_lft_lr_data_line_numbers = 4;
+
+ vp9_top_lb = ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT);
+ vp9_top_lb += ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT);
+ vp9_top_lb += max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES) *
+ MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE,
+ DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) *
+ MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE,
+ DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) *
+ MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE);
+ vp9_top_lb = ALIGN(vp9_top_lb, DMA_ALIGNMENT);
+ vp9_top_lb += ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)),
+ DMA_ALIGNMENT) * fe_top_ctrl_line_numbers;
+ vp9_top_lb += ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_size),
+ DMA_ALIGNMENT) * (fe_top_data_luma_line_numbers +
+ fe_top_data_chroma_line_numbers);
+
+ num_lcu_per_pipe = (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipes) +
+ (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes);
+ vp9_fe_left_lb = ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) *
+ fe_lft_ctrl_line_numbers;
+ vp9_fe_left_lb += ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_ALIGNMENT) *
+ fe_lft_db_data_line_numbers) +
+ ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) +
+ ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) +
+ (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) *
+ fe_lft_lr_data_line_numbers));
+ vp9_fe_left_lb = vp9_fe_left_lb * num_vpp_pipes;
+
+ vp9_se_left_lb = ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height),
+ DMA_ALIGNMENT);
+ dpb_opb = size_dpb_opb(frame_height, lcu_size);
+ vp9d_qp = ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
+
+ return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) +
+ (dpb_opb * num_vpp_pipes) + vp9d_qp;
+}
+
+static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
+ bool is_opb, u32 num_vpp_pipes)
+{
+ u32 lb_size = hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
+ u32 dpb_obp_size = 0, lcu_size = 64;
+
+ if (is_opb)
+ dpb_obp_size = size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes;
+
+ return lb_size + dpb_obp_size;
+}
+
+static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
+ struct v4l2_format *f = inst->fmt_src;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+ bool is_opb = false;
+
+ if (iris_split_mode_enabled(inst))
+ is_opb = true;
+
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
+ num_vpp_pipes);
+
+ return 0;
+}
+
+static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled)
+{
+ return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INFO *
+ H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF *
+ (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) +
+ rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT);
+}
+
+static u32 hfi_vpu4x_buffer_persist_vp9d(void)
+{
+ return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
+ (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) +
+ ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) +
+ ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) +
+ ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) +
+ ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X, DMA_ALIGNMENT) +
+ HDR10_HIST_EXTRADATA_SIZE;
+}
+
+static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
+{
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_persist_h264d();
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_vpu4x_buffer_persist_h265d(0);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_vpu4x_buffer_persist_vp9d();
+
+ return 0;
+}
+
+static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc,
+ u32 frame_width_coded, u32 frame_height_coded)
+{
+ u32 se_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
+ u32 se_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
+ ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
+ BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
+ ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
+ BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
+
+ se_llb_size = ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES);
+
+ if (num_vpp_pipes_enc > 1)
+ se_llb_size = ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES,
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT);
+}
+
+static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in_lcus,
+ u32 frame_height_coded, u32 frame_width_coded)
+{
+ u32 num_pixel_10_bit = 3, num_pixel_8_bit = 2, num_pixel_te_llb = 3;
+ u32 te_llb_col_rc_size = ALIGN(32 * width_in_lcus / num_vpp_pipes_enc,
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+ u32 te_tlb_recon_data_size = ALIGN((is_ten_bit ? num_pixel_10_bit : num_pixel_8_bit) *
+ frame_width_coded, DMA_ALIGNMENT);
+ u32 te_llb_recon_data_size = ((1 + is_ten_bit) * num_pixel_te_llb * frame_height_coded +
+ num_vpp_pipes_enc - 1) / num_vpp_pipes_enc;
+ te_llb_recon_data_size = ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_data_size,
+ DMA_ALIGNMENT);
+}
+
+static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit)
+{
+ u32 num_pixels_fe_tlb_10_bit = 128, num_pixels_fe_tlb_8_bit = 64;
+
+ return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) :
+ (size_per_lcu * num_pixels_fe_tlb_8_bit);
+}
+
+static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc,
+ u32 frame_height_coded, u32 frame_width_coded)
+{
+ u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width,
+ fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size,
+ fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size,
+ fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size,
+ fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size,
+ fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu;
+ u32 fe_sdc_data_per_block = 16, se_ctrl_data_per_block = 2020;
+
+ log2_lcu_size = (standard == HFI_CODEC_ENCODE_HEVC) ? 5 : 4;
+ num_cu_in_height_pipe = ((frame_height_coded >> log2_lcu_size) + num_vpp_pipes_enc - 1) /
+ num_vpp_pipes_enc;
+ num_cu_in_width = frame_width_coded >> log2_lcu_size;
+
+ size_per_lcu = 2;
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
+ fb_llb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_ctrl_size = ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = (1 << (log2_lcu_size - 3));
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
+ fb_llb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_luma_size = ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = ((1 << (log2_lcu_size - 4)) * 2);
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
+ fb_llb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_db_chroma_size = ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ size_per_lcu = 1;
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
+ fb_tlb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+ fb_llb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
+ fb_llb_sao_ctrl_size = fb_llb_sao_ctrl_size * num_vpp_pipes_enc;
+ fb_tlb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ size_per_lcu = ((1 << (log2_lcu_size - 3)) + 1);
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
+ fb_tlb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ size_per_lcu = (2 * ((1 << (log2_lcu_size - 4)) + 1));
+ fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
+ fb_tlb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
+
+ fb_llb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
+ fb_llb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
+ fb_tlb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES;
+ fb_tlb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES;
+ fb_lb_top_sdc_size = ALIGN((fe_sdc_data_per_block * (frame_width_coded >> 5)),
+ DMA_ALIGNMENT);
+ fb_lb_se_ctrl_size = ALIGN((se_ctrl_data_per_block * (frame_width_coded >> 5)),
+ DMA_ALIGNMENT);
+
+ return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size +
+ fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size +
+ fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size +
+ fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size +
+ fb_lb_top_sdc_size + fb_lb_se_ctrl_size;
+}
+
+static u32 size_md_lb(u32 standard, u32 frame_width_coded,
+ u32 frame_height_coded, u32 num_vpp_pipes_enc)
+{
+ u32 md_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
+ u32 md_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
+ ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
+ BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
+ ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
+ BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
+
+ md_llb_size = ALIGN(md_llb_size, BUFFER_ALIGNMENT_32_BYTES);
+
+ if (num_vpp_pipes_enc > 1)
+ md_llb_size = ALIGN(md_llb_size + BUFFER_ALIGNMENT_512_BYTES,
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ md_llb_size = ALIGN(md_llb_size, DMA_ALIGNMENT);
+
+ return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT);
+}
+
+static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded,
+ u32 frame_height_coded)
+{
+ u32 opb_packet_bytes = 128, opb_bpp = 128, opb_size_per_row = 6;
+ u32 dma_opb_wr_tlb_y_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
+ u32 dma_opb_wr_tlb_uv_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
+ u32 dma_opb_wr2_tlb_y_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+ u32 dma_opb_wr2_tlb_uv_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
+ DMA_ALIGNMENT) * num_vpp_pipes_enc;
+
+ dma_opb_wr2_tlb_y_size = max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_size << 1);
+ dma_opb_wr2_tlb_uv_size = max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_uv_size << 1);
+
+ return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2_tlb_y_size +
+ dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT);
+}
+
+static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height,
+ bool is_ten_bit, u32 num_vpp_pipes_enc,
+ u32 lcu_size, u32 standard)
+{
+ u32 width_in_lcus = (frame_width + lcu_size - 1) / lcu_size;
+ u32 height_in_lcus = (frame_height + lcu_size - 1) / lcu_size;
+ u32 frame_width_coded = width_in_lcus * lcu_size;
+ u32 frame_height_coded = height_in_lcus * lcu_size;
+
+ u32 se_lb_size = size_se_lb(standard, num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+ u32 te_lb_size = size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcus,
+ frame_height_coded, frame_width_coded);
+ u32 fe_lb_size = size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, frame_height_coded,
+ frame_width_coded);
+ u32 md_lb_size = size_md_lb(standard, frame_width_coded, frame_height_coded,
+ num_vpp_pipes_enc);
+ u32 dma_opb_lb_size = size_dma_opb_lb(num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+ u32 dse_lb_size = ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_ALIGNMENT);
+ u32 size_vpss_lb_enc = size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_width_coded,
+ frame_height_coded);
+
+ return se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_size +
+ dse_lb_size + size_vpss_lb_enc;
+}
+
+static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ u32 lcu_size = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
+ struct v4l2_format *f = inst->fmt_dst;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+
+ return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes,
+ lcu_size, inst->codec);
+}
+
static int output_min_count(struct iris_inst *inst)
{
int output_min_count = 4;
@@ -1503,6 +1804,50 @@ u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
return size;
}
+u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
+{
+ const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
+ u32 size = 0, buf_type_handle_size = 0, i;
+
+ static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_dec_bin_size },
+ {BUF_COMV, iris_vpu_dec_comv_size },
+ {BUF_NON_COMV, iris_vpu_dec_non_comv_size },
+ {BUF_LINE, iris_vpu4x_dec_line_size },
+ {BUF_PERSIST, iris_vpu4x_dec_persist_size },
+ {BUF_DPB, iris_vpu_dec_dpb_size },
+ {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
+ };
+
+ static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_enc_bin_size },
+ {BUF_COMV, iris_vpu_enc_comv_size },
+ {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
+ {BUF_LINE, iris_vpu4x_enc_line_size },
+ {BUF_ARP, iris_vpu_enc_arp_size },
+ {BUF_VPSS, iris_vpu_enc_vpss_size },
+ {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
+ {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
+ };
+
+ if (inst->domain == DECODER) {
+ buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
+ buf_type_handle_arr = dec_internal_buf_type_handle;
+ } else if (inst->domain == ENCODER) {
+ buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
+ buf_type_handle_arr = enc_internal_buf_type_handle;
+ }
+
+ for (i = 0; i < buf_type_handle_size; i++) {
+ if (buf_type_handle_arr[i].type == buffer_type) {
+ size = buf_type_handle_arr[i].handle(inst);
+ break;
+ }
+ }
+
+ return size;
+}
+
static u32 internal_buffer_count(struct iris_inst *inst,
enum iris_buffer_type buffer_type)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..15037e99914afc19de9f0d38eb778ef63363463b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
@@ -47,7 +47,12 @@ struct iris_inst;
#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4)
#define VP9_PROB_TABLE_SIZE (3840)
#define VP9_FRAME_INFO_BUF_SIZE (6144)
+#define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400)
+#define BUFFER_ALIGNMENT_16_BYTES 16
#define BUFFER_ALIGNMENT_32_BYTES 32
+#define BUFFER_ALIGNMENT_64_BYTES 64
+#define BUFFER_ALIGNMENT_256_BYTES 256
+#define BUFFER_ALIGNMENT_512_BYTES 512
#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
#define MAX_SUPERFRAME_HEADER_LEN (34)
#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
@@ -66,6 +71,8 @@ struct iris_inst;
#define H265_CABAC_HDR_RATIO_HD_TOT 2
#define H265_CABAC_RES_RATIO_HD_TOT 2
#define SIZE_H265D_VPP_CMD_PER_BUF (256)
+#define SIZE_THREE_DIMENSION_USERDATA 768
+#define SIZE_H265D_ARP 9728
#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1
@@ -76,6 +83,9 @@ struct iris_inst;
#define SIZE_H264D_HW_PIC_T (BIT(11))
+#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96
+#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192
+
#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
@@ -96,6 +106,10 @@ struct iris_inst;
#define HFI_BUFFER_ARP_ENC 204800
+#define LOG2_16 4
+#define LOG2_32 5
+#define LLB_UNIT_SIZE 16
+
#define MAX_WIDTH 4096
#define MAX_HEIGHT 2304
#define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
@@ -148,6 +162,7 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
+u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 5/8] media: iris: Move vpu register defines to common header file
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (3 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:27 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
` (4 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Some of vpu4 register defines are common with vpu3x. Move those into the
common register defines header. This is done to reuse the defines for
vpu4 in subsequent patch which enables the power sequence for vpu4.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
.../platform/qcom/iris/iris_vpu_register_defines.h | 32 +++++++++++++++++++
3 files changed, 32 insertions(+), 59 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 339776a0b4672e246848c3a6a260eb83c7da6a60..0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -11,48 +11,12 @@
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
-#define WRAPPER_TZ_BASE_OFFS 0x000C0000
-#define AON_BASE_OFFS 0x000E0000
-#define AON_MVP_NOC_RESET 0x0001F000
-
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
-#define REQ_POWER_DOWN_PREP BIT(0)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
-#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
-#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
-#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
-#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
#define CORE_CLK_RUN 0x0
/* VPU v3.5 */
#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT BIT(0)
-#define CTL_CLK_HALT BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH BIT(0)
-
-#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
-#define CORE_BRIDGE_SW_RESET BIT(0)
-#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
-
-#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
-#define MSK_CORE_POWER_ON BIT(1)
-
-#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
-#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
-
-#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
-
#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
#define SW_RESET BIT(0)
#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bbd999a41236dca5cf5700e452a6fed69f4fc922..a7b1fb8173e02d22e6f2af4ea170738c6408f65b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -11,9 +11,6 @@
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
-#define WRAPPER_TZ_BASE_OFFS 0x000C0000
-#define AON_BASE_OFFS 0x000E0000
-
#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
@@ -38,10 +35,6 @@
#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
#define HOST2XTENSA_INTR_ENABLE BIT(0)
-#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
-#define MSK_CORE_POWER_ON BIT(1)
-
#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
#define CPU_IC_SOFTINT_H2A_SHFT 0x0
@@ -53,23 +46,7 @@
#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
-
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT BIT(0)
-#define CTL_CLK_HALT BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
-#define REQ_POWER_DOWN_PREP BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
static void iris_vpu_interrupt_init(struct iris_core *core)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..bfe7ecceda894f6464970f9db2578c92dcb6c1ad 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -9,9 +9,41 @@
#define VCODEC_BASE_OFFS 0x00000000
#define CPU_BASE_OFFS 0x000A0000
#define WRAPPER_BASE_OFFS 0x000B0000
+#define AON_BASE_OFFS 0x000E0000
+#define AON_MVP_NOC_RESET 0x0001F000
+#define WRAPPER_TZ_BASE_OFFS 0x000C0000
+
+#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
+#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
+#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
+#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
+#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
+#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
+
+#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
+#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
+#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
+
+#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
+#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
+#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
+#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
+#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
+
+#define CORE_BRIDGE_SW_RESET BIT(0)
+#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
+#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
+#define MSK_CORE_POWER_ON BIT(1)
+#define CTL_AXI_CLK_HALT BIT(0)
+#define CTL_CLK_HALT BIT(1)
+#define REQ_POWER_DOWN_PREP BIT(0)
+#define RESET_HIGH BIT(0)
+#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
+#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
+#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (4 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:29 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
` (3 subsequent siblings)
9 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Some of the sequence and calculations for vpu4 is identical to vpu35,
namely power sequence for vpu controller and the clock frequency
calculation. Move those to common file that can be shared for both vpu35
and vpu4. This patch prepares for power sequence for vpu4 which is added
in subsequent patch.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu3x.c | 159 +--------------------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 143 ++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 4 +
3 files changed, 153 insertions(+), 153 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d..3abfb74dbb10974c8fe3cedaf67e8b4fca421015 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -12,8 +12,6 @@
#include "iris_vpu_register_defines.h"
#define CORE_CLK_RUN 0x0
-/* VPU v3.5 */
-#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
@@ -22,8 +20,6 @@
#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
#define NOC_HALT BIT(0)
#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28)
-#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
-#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
{
@@ -268,155 +264,12 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
}
-static int iris_vpu35_power_off_controller(struct iris_core *core)
-{
- u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
- unsigned int count = 0;
- u32 val = 0;
- bool handshake_done, handshake_busy;
- int ret;
-
- writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
-
- writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
-
- ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
- val, val & BIT(0), 200, 2000);
- if (ret)
- goto disable_power;
-
- writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
-
- /* Retry up to 1000 times as recommended by hardware documentation */
- do {
- /* set MNoC to low power */
- writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- udelay(15);
-
- val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
-
- handshake_done = val & NOC_LPI_STATUS_DONE;
- handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
-
- if (handshake_done || !handshake_busy)
- break;
-
- writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- udelay(15);
-
- } while (++count < 1000);
-
- if (!handshake_done && handshake_busy)
- dev_err(core->dev, "LPI handshake timeout\n");
-
- ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
- val, val & BIT(0), 200, 2000);
- if (ret)
- goto disable_power;
-
- writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
-
- writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
-
- ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
- val, val == 0, 200, 2000);
- if (ret)
- goto disable_power;
-
-disable_power:
- iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
- iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
-
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
-
- reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
-
- return 0;
-}
-
-static int iris_vpu35_power_on_controller(struct iris_core *core)
-{
- int ret;
-
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
- if (ret)
- return ret;
-
- ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
- if (ret)
- goto err_disable_power;
-
- ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
- if (ret)
- goto err_disable_axi1_clk;
-
- ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
- if (ret)
- goto err_disable_ctrl_free_clk;
-
- return 0;
-
-err_disable_ctrl_free_clk:
- iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
-err_disable_axi1_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
-err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
-
- return ret;
-}
-
-static void iris_vpu35_program_bootup_registers(struct iris_core *core)
-{
- writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
-}
-
-static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size)
-{
- struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
- struct v4l2_format *inp_f = inst->fmt_src;
- u32 height, width, mbs_per_second, mbpf;
- u64 fw_cycles, fw_vpp_cycles;
- u64 vsp_cycles, vpp_cycles;
- u32 fps = DEFAULT_FPS;
-
- width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
- height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
-
- mbpf = NUM_MBS_PER_FRAME(height, width);
- mbs_per_second = mbpf * fps;
-
- fw_cycles = fps * caps->mb_cycles_fw;
- fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
-
- vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
- /* 21 / 20 is minimum overhead factor */
- vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
-
- /* 1.059 is multi-pipe overhead */
- if (inst->fw_caps[PIPE].value > 1)
- vpp_cycles += div_u64(vpp_cycles * 59, 1000);
-
- vsp_cycles = fps * data_size * 8;
- vsp_cycles = div_u64(vsp_cycles, 2);
- /* VSP FW overhead 1.05 */
- vsp_cycles = div_u64(vsp_cycles * 21, 20);
-
- if (inst->fw_caps[STAGE].value == STAGE_1)
- vsp_cycles = vsp_cycles * 3;
-
- return max3(vpp_cycles, vsp_cycles, fw_cycles);
-}
-
const struct vpu_ops iris_vpu3_ops = {
.power_off_hw = iris_vpu3_power_off_hardware,
.power_on_hw = iris_vpu_power_on_hw,
.power_off_controller = iris_vpu_power_off_controller,
.power_on_controller = iris_vpu_power_on_controller,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
const struct vpu_ops iris_vpu33_ops = {
@@ -424,14 +277,14 @@ const struct vpu_ops iris_vpu33_ops = {
.power_on_hw = iris_vpu_power_on_hw,
.power_off_controller = iris_vpu33_power_off_controller,
.power_on_controller = iris_vpu_power_on_controller,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
const struct vpu_ops iris_vpu35_ops = {
.power_off_hw = iris_vpu35_power_off_hw,
.power_on_hw = iris_vpu35_power_on_hw,
- .power_off_controller = iris_vpu35_power_off_controller,
- .power_on_controller = iris_vpu35_power_on_controller,
- .program_bootup_registers = iris_vpu35_program_bootup_registers,
- .calc_freq = iris_vpu3x_calculate_frequency,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index a7b1fb8173e02d22e6f2af4ea170738c6408f65b..dd0990d143a624d83e241d9970297ce1abe37f74 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -8,6 +8,7 @@
#include <linux/reset.h>
#include "iris_core.h"
+#include "iris_instance.h"
#include "iris_vpu_common.h"
#include "iris_vpu_register_defines.h"
@@ -48,6 +49,10 @@
#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
+#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
+#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
+#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
+
static void iris_vpu_interrupt_init(struct iris_core *core)
{
u32 mask_val;
@@ -309,6 +314,144 @@ int iris_vpu_power_on_hw(struct iris_core *core)
return ret;
}
+int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
+{
+ u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
+ bool handshake_done, handshake_busy;
+ u32 count = 0, val = 0;
+ int ret;
+
+ writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
+
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
+
+ ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
+ val, val & BIT(0), 200, 2000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
+
+ /* Retry up to 1000 times as recommended by hardware documentation */
+ do {
+ /* set MNoC to low power */
+ writel(REQ_POWER_DOWN_PREP, core->reg_base +
+ AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
+
+ handshake_done = val & NOC_LPI_STATUS_DONE;
+ handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
+ val, val & BIT(0), 200, 2000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
+
+ writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
+
+ readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
+ val, val == 0, 200, 2000);
+
+disable_power:
+ iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+ iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
+
+ return 0;
+}
+
+int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
+ if (ret)
+ goto err_disable_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
+ if (ret)
+ goto err_disable_axi1_clk;
+
+ ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
+ if (ret)
+ goto err_disable_ctrl_free_clk;
+
+ return 0;
+
+err_disable_ctrl_free_clk:
+ iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
+err_disable_axi1_clk:
+ iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+err_disable_power:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ return ret;
+}
+
+void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core)
+{
+ writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
+}
+
+u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size)
+{
+ struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
+ struct v4l2_format *inp_f = inst->fmt_src;
+ u32 height, width, mbs_per_second, mbpf;
+ u64 fw_cycles, fw_vpp_cycles;
+ u64 vsp_cycles, vpp_cycles;
+ u32 fps = DEFAULT_FPS;
+
+ width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
+ height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
+
+ mbpf = NUM_MBS_PER_FRAME(height, width);
+ mbs_per_second = mbpf * fps;
+
+ fw_cycles = fps * caps->mb_cycles_fw;
+ fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
+
+ vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
+ /* 21 / 20 is minimum overhead factor */
+ vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
+
+ /* 1.059 is multi-pipe overhead */
+ if (inst->fw_caps[PIPE].value > 1)
+ vpp_cycles += div_u64(vpp_cycles * 59, 1000);
+
+ vsp_cycles = fps * data_size * 8;
+ vsp_cycles = div_u64(vsp_cycles, 2);
+ /* VSP FW overhead 1.05 */
+ vsp_cycles = div_u64(vsp_cycles * 21, 20);
+
+ if (inst->fw_caps[STAGE].value == STAGE_1)
+ vsp_cycles = vsp_cycles * 3;
+
+ return max3(vpp_cycles, vsp_cycles, fw_cycles);
+}
+
int iris_vpu_power_on(struct iris_core *core)
{
u32 freq;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index d636e287457adf0c44540af5c85cfa69decbca8b..7cf4304604cca590544a938c7e811c202cea3d93 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -33,5 +33,9 @@ int iris_vpu_power_on(struct iris_core *core);
int iris_vpu_power_off_controller(struct iris_core *core);
void iris_vpu_power_off_hw(struct iris_core *core);
void iris_vpu_power_off(struct iris_core *core);
+int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core);
+int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core);
+void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core);
+u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size);
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (5 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
` (2 subsequent siblings)
9 siblings, 0 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Add power sequence for vpu4 by reusing from previous generation wherever
possible. Hook up vpu4 op with vpu4 specific implemtation or resue from
earlier generation wherever feasible, like clock calculation in this
case.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 7 +
drivers/media/platform/qcom/iris/iris_vpu4x.c | 358 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
4 files changed, 367 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 13270cd6d899852dded675b33d37f5919b81ccba..1446f5732ab51db85ea4f52636d29e36d82b7a8f 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -22,6 +22,7 @@ qcom-iris-objs += iris_buffer.o \
iris_venc.o \
iris_vpu2.o \
iris_vpu3x.o \
+ iris_vpu4x.o \
iris_vpu_buffer.o \
iris_vpu_common.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index ae49e95ba2252fc1442f7c81d8010dbfd86da0da..d6d4a9fdfc189797f903dfeb56d931741b405ee2 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -54,6 +54,10 @@ enum platform_clk_type {
IRIS_AXI1_CLK,
IRIS_CTRL_FREERUN_CLK,
IRIS_HW_FREERUN_CLK,
+ IRIS_BSE_HW_CLK,
+ IRIS_VPP0_HW_CLK,
+ IRIS_VPP1_HW_CLK,
+ IRIS_APV_HW_CLK,
};
struct platform_clk_data {
@@ -188,6 +192,9 @@ struct icc_vote_data {
enum platform_pm_domain_type {
IRIS_CTRL_POWER_DOMAIN,
IRIS_HW_POWER_DOMAIN,
+ IRIS_VPP0_HW_POWER_DOMAIN,
+ IRIS_VPP1_HW_POWER_DOMAIN,
+ IRIS_APV_HW_POWER_DOMAIN,
};
struct iris_platform_data {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
new file mode 100644
index 0000000000000000000000000000000000000000..fa72f16ac38dcbc061698e3d496a1d2bbf17be27
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+
+#include "iris_instance.h"
+#include "iris_vpu_common.h"
+#include "iris_vpu_register_defines.h"
+
+#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST (AON_MVP_NOC_RESET + 0x08)
+#define CPU_CS_APV_BRIDGE_SYNC_RESET (CPU_BASE_OFFS + 0x174)
+#define MVP_NOC_RESET_REQ_MASK 0x70103
+#define VPU_IDLE_BITS 0x7103
+#define WRAPPER_EFUSE_MONITOR (WRAPPER_BASE_OFFS + 0x08)
+
+#define APV_CLK_HALT BIT(1)
+#define CORE_CLK_HALT BIT(0)
+#define CORE_PWR_ON BIT(1)
+#define DISABLE_VIDEO_APV_BIT BIT(27)
+#define DISABLE_VIDEO_VPP1_BIT BIT(28)
+#define DISABLE_VIDEO_VPP0_BIT BIT(29)
+
+static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 efuse_value)
+{
+ int ret;
+
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ return ret;
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_hw_domain_mode;
+ }
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_vpp0_domain_mode;
+ }
+
+ if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) {
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
+ [IRIS_APV_HW_POWER_DOMAIN], hw_mode);
+ if (ret)
+ goto restore_vpp1_domain_mode;
+ }
+
+ return 0;
+
+restore_vpp1_domain_mode:
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN],
+ !hw_mode);
+restore_vpp0_domain_mode:
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
+ !hw_mode);
+restore_hw_domain_mode:
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);
+
+ return ret;
+}
+
+static int iris_vpu4x_power_on_apv(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_APV_HW_CLK);
+ if (ret)
+ goto disable_apv_hw_power_domain;
+
+ return 0;
+
+disable_apv_hw_power_domain:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static void iris_vpu4x_power_off_apv(struct iris_core *core)
+{
+ bool handshake_done, handshake_busy;
+ u32 value, count = 0;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ if (value & APV_CLK_HALT)
+ writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ do {
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
+
+ handshake_done = value & NOC_LPI_STATUS_DONE;
+ handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ writel(0x080200, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value & 0x080200, 200, 2000);
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == 0x0, 200, 2000);
+
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+
+ iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+}
+
+static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core)
+{
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
+}
+
+static void iris_vpu4x_ahb_sync_reset_hardware(struct iris_core *core)
+{
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+}
+
+static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_value)
+{
+ int ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ if (ret)
+ goto disable_axi_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ if (ret)
+ goto disable_hw_free_run_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK);
+ if (ret)
+ goto disable_hw_clock;
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = iris_prepare_enable_clock(core, IRIS_VPP0_HW_CLK);
+ if (ret)
+ goto disable_bse_hw_clock;
+ }
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = iris_prepare_enable_clock(core, IRIS_VPP1_HW_CLK);
+ if (ret)
+ goto disable_vpp0_hw_clock;
+ }
+
+ return 0;
+
+disable_vpp0_hw_clock:
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
+disable_bse_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
+disable_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+disable_hw_free_run_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+disable_axi_clock:
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+
+ return ret;
+}
+
+static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse_value)
+{
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_unprepare_clock(core, IRIS_VPP1_HW_CLK);
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
+
+ iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+}
+
+static int iris_vpu4x_power_on_hardware(struct iris_core *core)
+{
+ u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+ if (ret)
+ goto disable_hw_power_domain;
+ }
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+ if (ret)
+ goto disable_vpp0_power_domain;
+ }
+
+ ret = iris_vpu4x_enable_hardware_clocks(core, efuse_value);
+ if (ret)
+ goto disable_vpp1_power_domain;
+
+ if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) {
+ ret = iris_vpu4x_power_on_apv(core);
+ if (ret)
+ goto disable_hw_clocks;
+
+ iris_vpu4x_ahb_sync_reset_apv(core);
+ }
+
+ iris_vpu4x_ahb_sync_reset_hardware(core);
+
+ ret = iris_vpu4x_genpd_set_hwmode(core, true, efuse_value);
+ if (ret)
+ goto disable_apv_power_domain;
+
+ return 0;
+
+disable_apv_power_domain:
+ if (!(efuse_value & DISABLE_VIDEO_APV_BIT))
+ iris_vpu4x_power_off_apv(core);
+disable_hw_clocks:
+ iris_vpu4x_disable_hardware_clocks(core, efuse_value);
+disable_vpp1_power_domain:
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+disable_vpp0_power_domain:
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+disable_hw_power_domain:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static void iris_vpu4x_power_off_hardware(struct iris_core *core)
+{
+ u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
+ bool handshake_done, handshake_busy;
+ u32 value, count = 0;
+
+ iris_vpu4x_genpd_set_hwmode(core, false, efuse_value);
+
+ if (!(efuse_value & DISABLE_VIDEO_APV_BIT))
+ iris_vpu4x_power_off_apv(core);
+
+ value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);
+
+ if (!(value & CORE_PWR_ON))
+ goto disable_clocks_and_power;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ if (value & CORE_CLK_HALT)
+ writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN, value,
+ value & VPU_IDLE_BITS, 2000, 20000);
+
+ do {
+ writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+ value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
+
+ handshake_done = value & NOC_LPI_STATUS_DONE;
+ handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
+
+ if (handshake_done || !handshake_busy)
+ break;
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ usleep_range(10, 20);
+
+ } while (++count < 1000);
+
+ if (!handshake_done && handshake_busy)
+ dev_err(core->dev, "LPI handshake timeout\n");
+
+ writel(MVP_NOC_RESET_REQ_MASK, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == MVP_NOC_RESET_REQ_MASK, 200, 2000);
+
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
+ writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
+ readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK,
+ value, value == 0x0, 200, 2000);
+
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
+disable_clocks_and_power:
+ iris_vpu4x_disable_hardware_clocks(core, efuse_value);
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP1_HW_POWER_DOMAIN]);
+
+ if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
+ [IRIS_VPP0_HW_POWER_DOMAIN]);
+
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+}
+
+const struct vpu_ops iris_vpu4x_ops = {
+ .power_off_hw = iris_vpu4x_power_off_hardware,
+ .power_on_hw = iris_vpu4x_power_on_hardware,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 7cf4304604cca590544a938c7e811c202cea3d93..f6dffc613b822341fb21e12de6b1395202f62cde 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops;
extern const struct vpu_ops iris_vpu3_ops;
extern const struct vpu_ops iris_vpu33_ops;
extern const struct vpu_ops iris_vpu35_ops;
+extern const struct vpu_ops iris_vpu4x_ops;
struct vpu_ops {
void (*power_off_hw)(struct iris_core *core);
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v2 8/8] media: iris: Add platform data for kaanapali
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (6 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
@ 2025-10-17 14:16 ` Vikash Garodia
2025-10-21 23:39 ` Bryan O'Donoghue
2025-10-22 15:20 ` Bryan O'Donoghue
2025-10-17 14:36 ` [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Nicolas Dufresne
2025-10-22 17:26 ` Konrad Dybcio
9 siblings, 2 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-17 14:16 UTC (permalink / raw)
To: Dikshita Agarwal, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Vikash Garodia
Add support for the kaanapali platform by re-using the SM8550
definitions and using the vpu4 ops.
Move the configurations that differs in a per-SoC platform
header, that will contain SoC specific data.
Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 1 +
.../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
.../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
4 files changed, 154 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index d6d4a9fdfc189797f903dfeb56d931741b405ee2..f77bad531f067f59b48c3e4caa40a463d454c47e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -41,6 +41,7 @@ enum pipe_type {
PIPE_4 = 4,
};
+extern struct iris_platform_data kaanapali_data;
extern struct iris_platform_data qcs8300_data;
extern struct iris_platform_data sm8250_data;
extern struct iris_platform_data sm8550_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..104c24fd47770dff770a5230cf957d78c89b01f7 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -12,6 +12,7 @@
#include "iris_vpu_buffer.h"
#include "iris_vpu_common.h"
+#include "iris_platform_kaanapali.h"
#include "iris_platform_qcs8300.h"
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
@@ -744,6 +745,91 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
BUF_SCRATCH_2,
};
+struct iris_platform_data kaanapali_data = {
+ .get_instance = iris_hfi_gen2_get_instance,
+ .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
+ .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
+ .get_vpu_buffer_size = iris_vpu4x_buf_size,
+ .vpu_ops = &iris_vpu4x_ops,
+ .set_preset_registers = iris_set_sm8550_preset_registers,
+ .icc_tbl = sm8550_icc_table,
+ .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
+ .clk_rst_tbl = kaanapali_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
+ .bw_tbl_dec = sm8550_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
+ .pmdomain_tbl = kaanapali_pmdomain_table,
+ .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
+ .opp_pd_tbl = sm8550_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
+ .clk_tbl = kaanapali_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
+ .opp_clk_tbl = kaanapali_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .fwname = "qcom/vpu/vpu40_p2_s7.mbn",
+ .pas_id = IRIS_PAS_ID,
+ .inst_caps = &platform_inst_cap_sm8550,
+ .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
+ .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
+ .tz_cp_config_data = tz_cp_config_kaanapali,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
+ .core_arch = VIDEO_ARCH_LX,
+ .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+ .ubwc_config = &ubwc_config_sm8550,
+ .num_vpp_pipe = 2,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((8192 * 4352) / 256) * 60,
+ .dec_input_config_params_default =
+ sm8550_vdec_input_config_params_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+ .dec_input_config_params_hevc =
+ sm8550_vdec_input_config_param_hevc,
+ .dec_input_config_params_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+ .dec_input_config_params_vp9 =
+ sm8550_vdec_input_config_param_vp9,
+ .dec_input_config_params_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_output_config_params =
+ sm8550_vdec_output_config_params,
+ .dec_output_config_params_size =
+ ARRAY_SIZE(sm8550_vdec_output_config_params),
+
+ .enc_input_config_params =
+ sm8550_venc_input_config_params,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8550_venc_input_config_params),
+ .enc_output_config_params =
+ sm8550_venc_output_config_params,
+ .enc_output_config_params_size =
+ ARRAY_SIZE(sm8550_venc_output_config_params),
+
+ .dec_input_prop = sm8550_vdec_subscribe_input_properties,
+ .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+ .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+ .dec_output_prop_avc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+ .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+ .dec_output_prop_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+ .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+ .dec_output_prop_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+
+ .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+
+ .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+ .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
+
struct iris_platform_data sm8550_data = {
.get_instance = iris_hfi_gen2_get_instance,
.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
new file mode 100644
index 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_PLATFORM_KAANAPALI_H__
+#define __IRIS_PLATFORM_KAANAPALI_H__
+
+#define VIDEO_REGION_VM0_SECURE_NP_ID 1
+#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
+
+static const char *const kaanapali_clk_reset_table[] = {
+ "bus0",
+ "bus1",
+ "core_freerun_reset",
+ "vcodec0_core_freerun_reset",
+};
+
+static const char *const kaanapali_pmdomain_table[] = {
+ "venus",
+ "vcodec0",
+ "vpp0",
+ "vpp1",
+ "apv",
+};
+
+static const struct platform_clk_data kaanapali_clk_table[] = {
+ { IRIS_AXI_CLK, "iface" },
+ { IRIS_CTRL_CLK, "core" },
+ { IRIS_HW_CLK, "vcodec0_core" },
+ { IRIS_AXI1_CLK, "iface1" },
+ { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
+ { IRIS_BSE_HW_CLK, "vcodec_bse" },
+ { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
+ { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
+ { IRIS_APV_HW_CLK, "vcodec_apv" },
+};
+
+static const char *const kaanapali_opp_clk_table[] = {
+ "vcodec0_core",
+ "vcodec_apv",
+ "vcodec_bse",
+ "core",
+ NULL,
+};
+
+static struct tz_cp_config tz_cp_config_kaanapali[] = {
+ {
+ .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+ {
+ .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x25800000,
+ .cp_nonpixel_size = 0xda400000,
+ },
+};
+
+#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ad82a62f8b923d818ffe77c131d7eb6da8c34002..a0902f3aaa1ca6021cfd414787da747a6dda1010 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = {
};
static const struct of_device_id iris_dt_match[] = {
+ {
+ .compatible = "qcom,kaanapali-iris",
+ .data = &kaanapali_data,
+ },
{
.compatible = "qcom,qcs8300-iris",
.data = &qcs8300_data,
--
2.34.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (7 preceding siblings ...)
2025-10-17 14:16 ` [PATCH v2 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
@ 2025-10-17 14:36 ` Nicolas Dufresne
2025-10-22 6:07 ` Vikash Garodia
2025-10-22 17:26 ` Konrad Dybcio
9 siblings, 1 reply; 32+ messages in thread
From: Nicolas Dufresne @ 2025-10-17 14:36 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Bryan O'Donoghue
[-- Attachment #1: Type: text/plain, Size: 638 bytes --]
Hi Vikash,
Le vendredi 17 octobre 2025 à 19:46 +0530, Vikash Garodia a
> [ 350.438406] qcom-iris 2000000.video-codec: invalid plane
> [ 350.447079] qcom-iris 2000000.video-codec: invalid plane
> [ 350.458821] qcom-iris 2000000.video-codec: invalid plane
> [ 350.465860] qcom-iris 2000000.video-codec: invalid plane
Just a highlight, the driver should only print stuff on default log level if
something is malfunctioning. uAPI miss-use should only be trace on loglevel
manually enabled by the developers. Mind fixing this up while at it ? Hopefully
this will be obvious to you next time you encounter it.
Nicolas
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-17 14:16 ` [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
@ 2025-10-18 15:58 ` Krzysztof Kozlowski
2025-10-21 18:55 ` Vikash Garodia
0 siblings, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-18 15:58 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 16:16, Vikash Garodia wrote:
> + clock-names:
> + items:
> + - const: iface
> + - const: core
> + - const: vcodec0_core
> + - const: iface1
> + - const: core_freerun
> + - const: vcodec0_core_freerun
> + - const: vcodec_bse
> + - const: vcodec_vpp0
> + - const: vcodec_vpp1
> + - const: vcodec_apv
> +
> + dma-coherent: true
> +
> + firmware-name:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: cpu-cfg
> + - const: video-mem
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + minItems: 3
> + maxItems: 8
I don't understand why this is flexible. Make it fixed size and anyway -
list the items.
I already asked this.
> +
> + memory-region:
> + minItems: 1
> + maxItems: 2
Same comment. I already asked this about iommus.
NAK, we should not repeat the same comment.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-18 15:58 ` Krzysztof Kozlowski
@ 2025-10-21 18:55 ` Vikash Garodia
2025-10-21 19:15 ` Krzysztof Kozlowski
2025-10-22 15:36 ` Konrad Dybcio
0 siblings, 2 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-21 18:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
> On 17/10/2025 16:16, Vikash Garodia wrote:
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: core
>> + - const: vcodec0_core
>> + - const: iface1
>> + - const: core_freerun
>> + - const: vcodec0_core_freerun
>> + - const: vcodec_bse
>> + - const: vcodec_vpp0
>> + - const: vcodec_vpp1
>> + - const: vcodec_apv
>> +
>> + dma-coherent: true
>> +
>> + firmware-name:
>> + maxItems: 1
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + items:
>> + - const: cpu-cfg
>> + - const: video-mem
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + iommus:
>> + minItems: 3
>> + maxItems: 8
>
> I don't understand why this is flexible. Make it fixed size and anyway -
> list the items.
kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
EL2 mode can list all of them, while boards running in EL1 can have only non
secure stream IDs. Min have the list of stream ids which can be enabled for all
type of boards, while max is for boards which can list all in HLOS given kernel
is in EL2 mode.
Below crash would be seen if boards running kernel in EL1 mode lists the secure
ones.
[ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
[ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
[ 1.361168] sp : ffff80008005b8f0
[ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
....
[ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
[ 1.361198] Call trace:
[ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
[ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
[ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
Could you please suggest on listing the iommu items ? I did not find the
relevant references in other bindings where flexible iommus is being listed.
>
> I already asked this.
>
>> +
>> + memory-region:
>> + minItems: 1
>> + maxItems: 2
>
> Same comment. I already asked this about iommus.
Same here, there aren't any bindings which lists for flexible memory-region.
Please suggest if there are any such references.
Regards,
Vikash
>
> NAK, we should not repeat the same comment.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-21 18:55 ` Vikash Garodia
@ 2025-10-21 19:15 ` Krzysztof Kozlowski
2025-10-21 21:07 ` Vikash Garodia
2025-10-22 15:36 ` Konrad Dybcio
1 sibling, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-21 19:15 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 21/10/2025 20:55, Vikash Garodia wrote:
>
> On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
>> On 17/10/2025 16:16, Vikash Garodia wrote:
>>> + clock-names:
>>> + items:
>>> + - const: iface
>>> + - const: core
>>> + - const: vcodec0_core
>>> + - const: iface1
>>> + - const: core_freerun
>>> + - const: vcodec0_core_freerun
>>> + - const: vcodec_bse
>>> + - const: vcodec_vpp0
>>> + - const: vcodec_vpp1
>>> + - const: vcodec_apv
>>> +
>>> + dma-coherent: true
>>> +
>>> + firmware-name:
>>> + maxItems: 1
>>> +
>>> + interconnects:
>>> + maxItems: 2
>>> +
>>> + interconnect-names:
>>> + items:
>>> + - const: cpu-cfg
>>> + - const: video-mem
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + iommus:
>>> + minItems: 3
>>> + maxItems: 8
>>
>> I don't understand why this is flexible. Make it fixed size and anyway -
>> list the items.
>
> kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
> EL2 mode can list all of them, while boards running in EL1 can have only non
> secure stream IDs. Min have the list of stream ids which can be enabled for all
> type of boards, while max is for boards which can list all in HLOS given kernel
> is in EL2 mode.
>
> Below crash would be seen if boards running kernel in EL1 mode lists the secure
> ones.
That has to be explained somewhere, e.g. comment, and still we need then
EL2 DTS in the kernel. I did not see such so far, but maybe I missed it
- can you link it?
>
> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
> [ 1.361168] sp : ffff80008005b8f0
> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
> ....
> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
> [ 1.361198] Call trace:
> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>
> Could you please suggest on listing the iommu items ? I did not find the
> relevant references in other bindings where flexible iommus is being listed.
Just like every other list property - clocks, resets, power-domains.
>
>>
>> I already asked this.
>>
>>> +
>>> + memory-region:
>>> + minItems: 1
>>> + maxItems: 2
>>
>> Same comment. I already asked this about iommus.
>
> Same here, there aren't any bindings which lists for flexible memory-region.
> Please suggest if there are any such references.
Because they do not matter for all other bindings, but it turned out
recently it might matter for this device.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-21 19:15 ` Krzysztof Kozlowski
@ 2025-10-21 21:07 ` Vikash Garodia
2025-10-22 6:04 ` Krzysztof Kozlowski
2025-10-22 9:37 ` Dmitry Baryshkov
0 siblings, 2 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-21 21:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/22/2025 12:45 AM, Krzysztof Kozlowski wrote:
> On 21/10/2025 20:55, Vikash Garodia wrote:
>>
>> On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
>>> On 17/10/2025 16:16, Vikash Garodia wrote:
>>>> + clock-names:
>>>> + items:
>>>> + - const: iface
>>>> + - const: core
>>>> + - const: vcodec0_core
>>>> + - const: iface1
>>>> + - const: core_freerun
>>>> + - const: vcodec0_core_freerun
>>>> + - const: vcodec_bse
>>>> + - const: vcodec_vpp0
>>>> + - const: vcodec_vpp1
>>>> + - const: vcodec_apv
>>>> +
>>>> + dma-coherent: true
>>>> +
>>>> + firmware-name:
>>>> + maxItems: 1
>>>> +
>>>> + interconnects:
>>>> + maxItems: 2
>>>> +
>>>> + interconnect-names:
>>>> + items:
>>>> + - const: cpu-cfg
>>>> + - const: video-mem
>>>> +
>>>> + interrupts:
>>>> + maxItems: 1
>>>> +
>>>> + iommus:
>>>> + minItems: 3
>>>> + maxItems: 8
>>>
>>> I don't understand why this is flexible. Make it fixed size and anyway -
>>> list the items.
>>
>> kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
>> EL2 mode can list all of them, while boards running in EL1 can have only non
>> secure stream IDs. Min have the list of stream ids which can be enabled for all
>> type of boards, while max is for boards which can list all in HLOS given kernel
>> is in EL2 mode.
>>
>> Below crash would be seen if boards running kernel in EL1 mode lists the secure
>> ones.
>
>
> That has to be explained somewhere, e.g. comment,
Sure, will add a description for iommus property explaining the same.
and still we need then
> EL2 DTS in the kernel. I did not see such so far, but maybe I missed it
> - can you link it?
>
EL2 DTS for kaanapali is not yet posted to handle secure SIDs. While it is in
development, describing the secure stream-ids would ensure to cover all the
hardware generated IDs.
>>
>> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
>> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
>> [ 1.361168] sp : ffff80008005b8f0
>> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
>> ....
>> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
>> [ 1.361198] Call trace:
>> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
>> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
>> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>>
>> Could you please suggest on listing the iommu items ? I did not find the
>> relevant references in other bindings where flexible iommus is being listed.
>
>
> Just like every other list property - clocks, resets, power-domains.
>
something like
iommu-names:
items:
- const: 0x1943
- const: 0x1940
...
given that one of vpu sub hardware generates multiple SIDs, if we go with sub
hardware name in the list, the names would be repeated.
>>
>>>
>>> I already asked this.
>>>
>>>> +
>>>> + memory-region:
>>>> + minItems: 1
>>>> + maxItems: 2
>>>
>>> Same comment. I already asked this about iommus.
>>
>> Same here, there aren't any bindings which lists for flexible memory-region.
>> Please suggest if there are any such references.
>
> Because they do not matter for all other bindings, but it turned out
> recently it might matter for this device.
memory-region:
minItems: 1
maxItems: 2
memory-region-names:
items:
- const video_mem
- const iris_resv
Regards,
Vikash
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 2/8] media: iris: Add support for multiple clock sources
2025-10-17 14:16 ` [PATCH v2 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
@ 2025-10-21 23:06 ` Bryan O'Donoghue
0 siblings, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:06 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> vpu4 depends on more than one clock source. Thus far hardware versions
> up to vpu3x have been clocked by a single source.
> This adds support for multiple clocks by,
> - Adding a lookup table
> - Configuring OPP table for video device with different video clocks
> - Setting OPP for multiple clocks during dev_pm_opp_set_opp()
>
> This patch extends the support for multiple clocks in driver, which
> would be used in subsequent patch for kaanapali, when the platform data
> is prepared.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../media/platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 9 +++++++++
> .../media/platform/qcom/iris/iris_platform_sm8250.c | 6 ++++++
> drivers/media/platform/qcom/iris/iris_power.c | 2 +-
> drivers/media/platform/qcom/iris/iris_probe.c | 20 ++++++++------------
> drivers/media/platform/qcom/iris/iris_resources.c | 16 ++++++++++++++--
> drivers/media/platform/qcom/iris/iris_resources.h | 1 +
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
> 8 files changed, 42 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 58d05e0a112eed25faea027a34c719c89d6c3897..df03de08c44839c1b6c137874eb7273c638d5f2c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -206,6 +206,7 @@ struct iris_platform_data {
> const char * const *opp_pd_tbl;
> unsigned int opp_pd_tbl_size;
> const struct platform_clk_data *clk_tbl;
> + const char * const *opp_clk_tbl;
> unsigned int clk_tbl_size;
> const char * const *clk_rst_tbl;
> unsigned int clk_rst_tbl_size;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 36d69cc73986b74534a2912524c8553970fd862e..fea800811a389a58388175c733ad31c4d9c636b0 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -633,6 +633,11 @@ static const struct platform_clk_data sm8550_clk_table[] = {
> {IRIS_HW_CLK, "vcodec0_core" },
> };
>
> +static const char * const sm8550_opp_clk_table[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> static struct ubwc_config_data ubwc_config_sm8550 = {
> .max_channels = 8,
> .mal_length = 32,
> @@ -756,6 +761,7 @@ struct iris_platform_data sm8550_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu30_p4.mbn",
> @@ -848,6 +854,7 @@ struct iris_platform_data sm8650_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu33_p4.mbn",
> @@ -930,6 +937,7 @@ struct iris_platform_data sm8750_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8750_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu35_p4.mbn",
> @@ -1017,6 +1025,7 @@ struct iris_platform_data qcs8300_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> .clk_tbl = sm8550_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 16486284f8acccf6a95a27f6003e885226e28f4d..1b1b6aa751106ee0b0bc71bb0df2e78340190e66 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -273,6 +273,11 @@ static const struct platform_clk_data sm8250_clk_table[] = {
> {IRIS_HW_CLK, "vcodec0_core" },
> };
>
> +static const char * const sm8250_opp_clk_table[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> static struct tz_cp_config tz_cp_config_sm8250 = {
> .cp_start = 0,
> .cp_size = 0x25800000,
> @@ -333,6 +338,7 @@ struct iris_platform_data sm8250_data = {
> .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
> .clk_tbl = sm8250_clk_table,
> .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
> + .opp_clk_tbl = sm8250_opp_clk_table,
> /* Upper bound of DMA address range */
> .dma_mask = 0xe0000000 - 1,
> .fwname = "qcom/vpu-1.0/venus.mbn",
> diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c
> index dbca42df0910fd3c0fb253dbfabf1afa2c3d32ad..91aa21d4070ebcebbe2ed127a03e5e49b9a2bd5c 100644
> --- a/drivers/media/platform/qcom/iris/iris_power.c
> +++ b/drivers/media/platform/qcom/iris/iris_power.c
> @@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst)
> }
>
> core->power.clk_freq = freq;
> - ret = dev_pm_opp_set_rate(core->dev, freq);
> + ret = iris_opp_set_rate(core->dev, freq);
> mutex_unlock(&core->lock);
>
> return ret;
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index 00e99be16e087c4098f930151fd76cd381d721ce..ad82a62f8b923d818ffe77c131d7eb6da8c34002 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -40,8 +40,6 @@ static int iris_init_icc(struct iris_core *core)
>
> static int iris_init_power_domains(struct iris_core *core)
> {
> - const struct platform_clk_data *clk_tbl;
> - u32 clk_cnt, i;
> int ret;
>
> struct dev_pm_domain_attach_data iris_pd_data = {
> @@ -56,6 +54,11 @@ static int iris_init_power_domains(struct iris_core *core)
> .pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
> };
>
> + struct dev_pm_opp_config iris_opp_clk_data = {
> + .clk_names = core->iris_platform_data->opp_clk_tbl,
> + .config_clks = dev_pm_opp_config_clks_simple,
> + };
> +
> ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
> if (ret < 0)
> return ret;
> @@ -64,16 +67,9 @@ static int iris_init_power_domains(struct iris_core *core)
> if (ret < 0)
> return ret;
>
> - clk_tbl = core->iris_platform_data->clk_tbl;
> - clk_cnt = core->iris_platform_data->clk_tbl_size;
> -
> - for (i = 0; i < clk_cnt; i++) {
> - if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
> - ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
> - if (ret)
> - return ret;
> - }
> - }
> + ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
> + if (ret)
> + return ret;
>
> return devm_pm_opp_of_add_table(core->dev);
> }
> diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
> index cf32f268b703c1c042a9bcf146e444fff4f4990d..939f6617f2631503fa8cb3e874b9de6b2fbe7b76 100644
> --- a/drivers/media/platform/qcom/iris/iris_resources.c
> +++ b/drivers/media/platform/qcom/iris/iris_resources.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/devfreq.h>
> #include <linux/interconnect.h>
> #include <linux/pm_domain.h>
> #include <linux/pm_opp.h>
> @@ -58,11 +59,22 @@ int iris_unset_icc_bw(struct iris_core *core)
> return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
> }
>
> +int iris_opp_set_rate(struct device *dev, unsigned long freq)
> +{
> + struct dev_pm_opp *opp __free(put_opp);
> +
> + opp = devfreq_recommended_opp(dev, &freq, 0);
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> +
> + return dev_pm_opp_set_opp(dev, opp);
> +}
> +
> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
> {
> int ret;
>
> - ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
> + ret = iris_opp_set_rate(core->dev, ULONG_MAX);
> if (ret)
> return ret;
>
> @@ -77,7 +89,7 @@ int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
> {
> int ret;
>
> - ret = dev_pm_opp_set_rate(core->dev, 0);
> + ret = iris_opp_set_rate(core->dev, 0);
> if (ret)
> return ret;
>
> diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
> index f723dfe5bd81a9c9db22d53bde4e18743d771210..6bfbd2dc6db095ec05e53c894e048285f82446c6 100644
> --- a/drivers/media/platform/qcom/iris/iris_resources.h
> +++ b/drivers/media/platform/qcom/iris/iris_resources.h
> @@ -8,6 +8,7 @@
>
> struct iris_core;
>
> +int iris_opp_set_rate(struct device *dev, unsigned long freq);
> int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
> int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
> int iris_unset_icc_bw(struct iris_core *core);
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..bbd999a41236dca5cf5700e452a6fed69f4fc922 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -266,7 +266,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
>
> void iris_vpu_power_off(struct iris_core *core)
> {
> - dev_pm_opp_set_rate(core->dev, 0);
> + iris_opp_set_rate(core->dev, 0);
> core->iris_platform_data->vpu_ops->power_off_hw(core);
> core->iris_platform_data->vpu_ops->power_off_controller(core);
> iris_unset_icc_bw(core);
> @@ -352,7 +352,7 @@ int iris_vpu_power_on(struct iris_core *core)
> freq = core->power.clk_freq ? core->power.clk_freq :
> (u32)ULONG_MAX;
>
> - dev_pm_opp_set_rate(core->dev, freq);
> + iris_opp_set_rate(core->dev, freq);
>
> core->iris_platform_data->set_preset_registers(core);
>
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-10-17 14:16 ` [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
@ 2025-10-21 23:25 ` Bryan O'Donoghue
2025-10-22 5:44 ` Vikash Garodia
0 siblings, 1 reply; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:25 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> Introduces vp4 buffer size calculation for both encoder and decoder.
> Reuse the buffer size calculation which are common, while adding the
> vpu4 ones separately.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 345 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 15 +
> 2 files changed, 360 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> index 4463be05ce165adef6b152eb0c155d2e6a7b3c36..8cc52d7aba3ffb968191519c1a1a10e326403205 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> @@ -1408,6 +1408,307 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
> return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
> }
>
> +static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
> +{
> + u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
> + u32 dpb_opb = 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT);
> + u32 num_luma_chrome_plane = 2;
> +
> + return dpb_opb = num_luma_chrome_plane * ALIGN(dpb_opb, DMA_ALIGNMENT);
return thing = someother-thing.
You must mean
return (num_luma_chrome_plane * ALIGN(dpb_opb, DMA_ALIGNMENT));
> +}
> +
> +static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp, num_lcu_per_pipe;
> + u32 lcu_size = 64, fe_top_ctrl_line_numbers = 3, fe_top_data_luma_line_numbers = 2,
> + fe_top_data_chroma_line_numbers = 3, fe_lft_ctrl_line_numbers = 4,
> + fe_lft_db_data_line_numbers = 2, fe_lft_lr_data_line_numbers = 4;
You can reduce this very long variable list to macro constants.
For example fe_lft_db_data_line_numbers doesn't vary so it shouldn't be
a variable.
> +
> + vp9_top_lb = ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT);
> + vp9_top_lb += ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT);
> + vp9_top_lb += max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES) *
> + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE,
> + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) *
> + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE,
> + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) *
> + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE);
> + vp9_top_lb = ALIGN(vp9_top_lb, DMA_ALIGNMENT);
> + vp9_top_lb += ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)),
> + DMA_ALIGNMENT) * fe_top_ctrl_line_numbers;
> + vp9_top_lb += ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_size),
> + DMA_ALIGNMENT) * (fe_top_data_luma_line_numbers +
> + fe_top_data_chroma_line_numbers);
> +
> + num_lcu_per_pipe = (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipes) +
> + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes);
> + vp9_fe_left_lb = ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) *
> + fe_lft_ctrl_line_numbers;
> + vp9_fe_left_lb += ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_ALIGNMENT) *
> + fe_lft_db_data_line_numbers) +
> + ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) +
> + ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) +
> + (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) *
> + fe_lft_lr_data_line_numbers));
> + vp9_fe_left_lb = vp9_fe_left_lb * num_vpp_pipes;
> +
> + vp9_se_left_lb = ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height),
> + DMA_ALIGNMENT);
> + dpb_opb = size_dpb_opb(frame_height, lcu_size);
> + vp9d_qp = ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
> +
> + return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) +
> + (dpb_opb * num_vpp_pipes) + vp9d_qp;
> +}
> +
> +static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
> + bool is_opb, u32 num_vpp_pipes)
> +{
> + u32 lb_size = hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
> + u32 dpb_obp_size = 0, lcu_size = 64;
> +
> + if (is_opb)
> + dpb_obp_size = size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes;
> +
> + return lb_size + dpb_obp_size;
> +}
> +
> +static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
> +{
> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> + u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
> + struct v4l2_format *f = inst->fmt_src;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> + bool is_opb = false;
> +
> + if (iris_split_mode_enabled(inst))
> + is_opb = true;
> +
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_VP9)
> + return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
> + num_vpp_pipes);
> +
> + return 0;
> +}
> +
> +static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled)
> +{
> + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INFO *
> + H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF *
> + (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) +
> + rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT);
> +}
> +
> +static u32 hfi_vpu4x_buffer_persist_vp9d(void)
> +{
> + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
> + (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) +
> + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) +
> + ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) +
> + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) +
> + ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X, DMA_ALIGNMENT) +
> + HDR10_HIST_EXTRADATA_SIZE;
> +}
> +
> +static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
> +{
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_persist_h264d();
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_vpu4x_buffer_persist_h265d(0);
> + else if (inst->codec == V4L2_PIX_FMT_VP9)
> + return hfi_vpu4x_buffer_persist_vp9d();
> +
> + return 0;
> +}
> +
> +static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc,
> + u32 frame_width_coded, u32 frame_height_coded)
> +{
> + u32 se_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
> + u32 se_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
> + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
> + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
> + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
> + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
> +
> + se_llb_size = ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES);
> +
> + if (num_vpp_pipes_enc > 1)
> + se_llb_size = ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES,
> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT);
> +}
> +
> +static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in_lcus,
> + u32 frame_height_coded, u32 frame_width_coded)
> +{
> + u32 num_pixel_10_bit = 3, num_pixel_8_bit = 2, num_pixel_te_llb = 3;
> + u32 te_llb_col_rc_size = ALIGN(32 * width_in_lcus / num_vpp_pipes_enc,
> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
> + u32 te_tlb_recon_data_size = ALIGN((is_ten_bit ? num_pixel_10_bit : num_pixel_8_bit) *
> + frame_width_coded, DMA_ALIGNMENT);
> + u32 te_llb_recon_data_size = ((1 + is_ten_bit) * num_pixel_te_llb * frame_height_coded +
> + num_vpp_pipes_enc - 1) / num_vpp_pipes_enc;
> + te_llb_recon_data_size = ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_data_size,
> + DMA_ALIGNMENT);
> +}
> +
> +static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit)
> +{
> + u32 num_pixels_fe_tlb_10_bit = 128, num_pixels_fe_tlb_8_bit = 64;
> +
> + return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) :
> + (size_per_lcu * num_pixels_fe_tlb_8_bit);
> +}
> +
> +static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc,
> + u32 frame_height_coded, u32 frame_width_coded)
> +{
> + u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width,
> + fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size,
> + fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size,
> + fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size,
> + fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size,
> + fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu;
> + u32 fe_sdc_data_per_block = 16, se_ctrl_data_per_block = 2020;
Again you can reduce this - at least a little bit
fe_sdc_data_per_block
se_ctrl_data_per_block
are const
> +
> + log2_lcu_size = (standard == HFI_CODEC_ENCODE_HEVC) ? 5 : 4;
> + num_cu_in_height_pipe = ((frame_height_coded >> log2_lcu_size) + num_vpp_pipes_enc - 1) /
> + num_vpp_pipes_enc;
> + num_cu_in_width = frame_width_coded >> log2_lcu_size;
> +
> + size_per_lcu = 2;
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
> + fb_llb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
> + fb_llb_db_ctrl_size = ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + size_per_lcu = (1 << (log2_lcu_size - 3));
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
> + fb_llb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
> + fb_llb_db_luma_size = ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + size_per_lcu = ((1 << (log2_lcu_size - 4)) * 2);
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
> + fb_llb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
> + fb_llb_db_chroma_size = ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + size_per_lcu = 1;
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
> + fb_tlb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
> + fb_llb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
> + fb_llb_sao_ctrl_size = fb_llb_sao_ctrl_size * num_vpp_pipes_enc;
> + fb_tlb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
> +
> + size_per_lcu = ((1 << (log2_lcu_size - 3)) + 1);
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
> + fb_tlb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
> +
> + size_per_lcu = (2 * ((1 << (log2_lcu_size - 4)) + 1));
> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
> + fb_tlb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
> +
> + fb_llb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
> + fb_llb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
> + fb_tlb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES;
> + fb_tlb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES;
> + fb_lb_top_sdc_size = ALIGN((fe_sdc_data_per_block * (frame_width_coded >> 5)),
> + DMA_ALIGNMENT);
> + fb_lb_se_ctrl_size = ALIGN((se_ctrl_data_per_block * (frame_width_coded >> 5)),
> + DMA_ALIGNMENT);
On the one hand lots of variables.
On the other hand I think the code is more readable with assigned names
instead of a big morass of return ALIGN(stuff) + ALIGN(other stuff).
Anyway I think you can reduce this enormomous variable list by at lest two.
u32 fe_sdc_data_per_block = 16, se_ctrl_data_per_block = 2020;
->
#define FE_SDC_DATA_PER_BLOCK 16
#define SE_CTRL_DATA_PER_BLOCK 2020
> + return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size +
> + fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size +
> + fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size +
> + fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size +
> + fb_lb_top_sdc_size + fb_lb_se_ctrl_size;
> +}
> +
> +static u32 size_md_lb(u32 standard, u32 frame_width_coded,
> + u32 frame_height_coded, u32 num_vpp_pipes_enc)
> +{
> + u32 md_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
> + u32 md_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
> + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
> + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
> + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
> + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
> +
> + md_llb_size = ALIGN(md_llb_size, BUFFER_ALIGNMENT_32_BYTES);
> +
> + if (num_vpp_pipes_enc > 1)
> + md_llb_size = ALIGN(md_llb_size + BUFFER_ALIGNMENT_512_BYTES,
> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + md_llb_size = ALIGN(md_llb_size, DMA_ALIGNMENT);
> +
> + return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT);
> +}
> +
> +static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded,
> + u32 frame_height_coded)
> +{
> + u32 opb_packet_bytes = 128, opb_bpp = 128, opb_size_per_row = 6;
> + u32 dma_opb_wr_tlb_y_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
> + u32 dma_opb_wr_tlb_uv_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
> + u32 dma_opb_wr2_tlb_y_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
> + u32 dma_opb_wr2_tlb_uv_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
> +
> + dma_opb_wr2_tlb_y_size = max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_size << 1);
> + dma_opb_wr2_tlb_uv_size = max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_uv_size << 1);
> +
> + return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2_tlb_y_size +
> + dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT);
> +}
> +
> +static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height,
> + bool is_ten_bit, u32 num_vpp_pipes_enc,
> + u32 lcu_size, u32 standard)
> +{
> + u32 width_in_lcus = (frame_width + lcu_size - 1) / lcu_size;
> + u32 height_in_lcus = (frame_height + lcu_size - 1) / lcu_size;
> + u32 frame_width_coded = width_in_lcus * lcu_size;
> + u32 frame_height_coded = height_in_lcus * lcu_size;
> +
> + u32 se_lb_size = size_se_lb(standard, num_vpp_pipes_enc, frame_width_coded,
> + frame_height_coded);
> + u32 te_lb_size = size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcus,
> + frame_height_coded, frame_width_coded);
> + u32 fe_lb_size = size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, frame_height_coded,
> + frame_width_coded);
> + u32 md_lb_size = size_md_lb(standard, frame_width_coded, frame_height_coded,
> + num_vpp_pipes_enc);
> + u32 dma_opb_lb_size = size_dma_opb_lb(num_vpp_pipes_enc, frame_width_coded,
> + frame_height_coded);
> + u32 dse_lb_size = ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_ALIGNMENT);
> + u32 size_vpss_lb_enc = size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_width_coded,
> + frame_height_coded);
> +
> + return se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_size +
> + dse_lb_size + size_vpss_lb_enc;
> +}
> +
> +static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst)
> +{
> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> + u32 lcu_size = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
> + struct v4l2_format *f = inst->fmt_dst;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> +
> + return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes,
> + lcu_size, inst->codec);
> +}
> +
> static int output_min_count(struct iris_inst *inst)
> {
> int output_min_count = 4;
> @@ -1503,6 +1804,50 @@ u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
> return size;
> }
>
> +u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
> +{
> + const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
> + u32 size = 0, buf_type_handle_size = 0, i;
> +
> + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
> + {BUF_BIN, iris_vpu_dec_bin_size },
> + {BUF_COMV, iris_vpu_dec_comv_size },
> + {BUF_NON_COMV, iris_vpu_dec_non_comv_size },
> + {BUF_LINE, iris_vpu4x_dec_line_size },
> + {BUF_PERSIST, iris_vpu4x_dec_persist_size },
> + {BUF_DPB, iris_vpu_dec_dpb_size },
> + {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
> + };
> +
> + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
> + {BUF_BIN, iris_vpu_enc_bin_size },
> + {BUF_COMV, iris_vpu_enc_comv_size },
> + {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
> + {BUF_LINE, iris_vpu4x_enc_line_size },
> + {BUF_ARP, iris_vpu_enc_arp_size },
> + {BUF_VPSS, iris_vpu_enc_vpss_size },
> + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
> + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
> + };
> +
> + if (inst->domain == DECODER) {
> + buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
> + buf_type_handle_arr = dec_internal_buf_type_handle;
> + } else if (inst->domain == ENCODER) {
> + buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
> + buf_type_handle_arr = enc_internal_buf_type_handle;
> + }
> +
> + for (i = 0; i < buf_type_handle_size; i++) {
> + if (buf_type_handle_arr[i].type == buffer_type) {
> + size = buf_type_handle_arr[i].handle(inst);
> + break;
> + }
> + }
> +
> + return size;
> +}
> +
> static u32 internal_buffer_count(struct iris_inst *inst,
> enum iris_buffer_type buffer_type)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> index 04f0b7400a1e4e1d274d690a2761b9e57778e8b7..15037e99914afc19de9f0d38eb778ef63363463b 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> @@ -47,7 +47,12 @@ struct iris_inst;
> #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4)
> #define VP9_PROB_TABLE_SIZE (3840)
> #define VP9_FRAME_INFO_BUF_SIZE (6144)
> +#define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400)
> +#define BUFFER_ALIGNMENT_16_BYTES 16
> #define BUFFER_ALIGNMENT_32_BYTES 32
> +#define BUFFER_ALIGNMENT_64_BYTES 64
> +#define BUFFER_ALIGNMENT_256_BYTES 256
> +#define BUFFER_ALIGNMENT_512_BYTES 512
> #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
> #define MAX_SUPERFRAME_HEADER_LEN (34)
> #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
> @@ -66,6 +71,8 @@ struct iris_inst;
> #define H265_CABAC_HDR_RATIO_HD_TOT 2
> #define H265_CABAC_RES_RATIO_HD_TOT 2
> #define SIZE_H265D_VPP_CMD_PER_BUF (256)
> +#define SIZE_THREE_DIMENSION_USERDATA 768
> +#define SIZE_H265D_ARP 9728
>
> #define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
> #define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1
> @@ -76,6 +83,9 @@ struct iris_inst;
>
> #define SIZE_H264D_HW_PIC_T (BIT(11))
>
> +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96
> +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192
> +
> #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
> #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
> #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
> @@ -96,6 +106,10 @@ struct iris_inst;
>
> #define HFI_BUFFER_ARP_ENC 204800
>
> +#define LOG2_16 4
> +#define LOG2_32 5
> +#define LLB_UNIT_SIZE 16
> +
> #define MAX_WIDTH 4096
> #define MAX_HEIGHT 2304
> #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
> @@ -148,6 +162,7 @@ static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
>
> u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> +u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
>
> #endif
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 5/8] media: iris: Move vpu register defines to common header file
2025-10-17 14:16 ` [PATCH v2 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
@ 2025-10-21 23:27 ` Bryan O'Donoghue
0 siblings, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:27 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> Some of vpu4 register defines are common with vpu3x. Move those into the
> common register defines header. This is done to reuse the defines for
> vpu4 in subsequent patch which enables the power sequence for vpu4.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 36 ----------------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 --------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 32 +++++++++++++++++++
> 3 files changed, 32 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,12 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -#define AON_MVP_NOC_RESET 0x0001F000
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> #define CORE_CLK_RUN 0x0
> /* VPU v3.5 */
> #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
>
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
>
> -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> -
> -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
> #define SW_RESET BIT(0)
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bbd999a41236dca5cf5700e452a6fed69f4fc922..a7b1fb8173e02d22e6f2af4ea170738c6408f65b 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,9 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -
> #define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
>
> #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> @@ -38,10 +35,6 @@
> #define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> #define HOST2XTENSA_INTR_ENABLE BIT(0)
>
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> #define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> #define CPU_IC_SOFTINT_H2A_SHFT 0x0
>
> @@ -53,23 +46,7 @@
> #define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> #define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
>
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -
> #define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..bfe7ecceda894f6464970f9db2578c92dcb6c1ad 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,41 @@
> #define VCODEC_BASE_OFFS 0x00000000
> #define CPU_BASE_OFFS 0x000A0000
> #define WRAPPER_BASE_OFFS 0x000B0000
> +#define AON_BASE_OFFS 0x000E0000
> +#define AON_MVP_NOC_RESET 0x0001F000
> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> +
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
>
> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> +
> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
>
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> +
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> +
> +#define CORE_BRIDGE_SW_RESET BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> +#define MSK_CORE_POWER_ON BIT(1)
> +#define CTL_AXI_CLK_HALT BIT(0)
> +#define CTL_CLK_HALT BIT(1)
> +#define REQ_POWER_DOWN_PREP BIT(0)
> +#define RESET_HIGH BIT(0)
> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
>
> #endif
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4
2025-10-17 14:16 ` [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
@ 2025-10-21 23:29 ` Bryan O'Donoghue
0 siblings, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:29 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> Some of the sequence and calculations for vpu4 is identical to vpu35,
> namely power sequence for vpu controller and the clock frequency
> calculation. Move those to common file that can be shared for both vpu35
> and vpu4. This patch prepares for power sequence for vpu4 which is added
> in subsequent patch.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 159 +--------------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 143 ++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 4 +
> 3 files changed, 153 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 0ac6373c33b7ced75ac94ac86a1a8fc303f28b5d..3abfb74dbb10974c8fe3cedaf67e8b4fca421015 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -12,8 +12,6 @@
> #include "iris_vpu_register_defines.h"
>
> #define CORE_CLK_RUN 0x0
> -/* VPU v3.5 */
> -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
>
> #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
>
> @@ -22,8 +20,6 @@
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> #define NOC_HALT BIT(0)
> #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28)
> -#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
> -#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
>
> static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
> {
> @@ -268,155 +264,12 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
> iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> }
>
> -static int iris_vpu35_power_off_controller(struct iris_core *core)
> -{
> - u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
> - unsigned int count = 0;
> - u32 val = 0;
> - bool handshake_done, handshake_busy;
> - int ret;
> -
> - writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
> -
> - writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> -
> - ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
> - val, val & BIT(0), 200, 2000);
> - if (ret)
> - goto disable_power;
> -
> - writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> -
> - /* Retry up to 1000 times as recommended by hardware documentation */
> - do {
> - /* set MNoC to low power */
> - writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> -
> - udelay(15);
> -
> - val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
> -
> - handshake_done = val & NOC_LPI_STATUS_DONE;
> - handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
> -
> - if (handshake_done || !handshake_busy)
> - break;
> -
> - writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> -
> - udelay(15);
> -
> - } while (++count < 1000);
> -
> - if (!handshake_done && handshake_busy)
> - dev_err(core->dev, "LPI handshake timeout\n");
> -
> - ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
> - val, val & BIT(0), 200, 2000);
> - if (ret)
> - goto disable_power;
> -
> - writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> -
> - writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
> -
> - ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
> - val, val == 0, 200, 2000);
> - if (ret)
> - goto disable_power;
> -
> -disable_power:
> - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> -
> - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> -
> - reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
> -
> - return 0;
> -}
> -
> -static int iris_vpu35_power_on_controller(struct iris_core *core)
> -{
> - int ret;
> -
> - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> - if (ret)
> - return ret;
> -
> - ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
> - if (ret)
> - goto err_disable_power;
> -
> - ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
> - if (ret)
> - goto err_disable_axi1_clk;
> -
> - ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
> - if (ret)
> - goto err_disable_ctrl_free_clk;
> -
> - return 0;
> -
> -err_disable_ctrl_free_clk:
> - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> -err_disable_axi1_clk:
> - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> -err_disable_power:
> - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> -
> - return ret;
> -}
> -
> -static void iris_vpu35_program_bootup_registers(struct iris_core *core)
> -{
> - writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
> -}
> -
> -static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size)
> -{
> - struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> - struct v4l2_format *inp_f = inst->fmt_src;
> - u32 height, width, mbs_per_second, mbpf;
> - u64 fw_cycles, fw_vpp_cycles;
> - u64 vsp_cycles, vpp_cycles;
> - u32 fps = DEFAULT_FPS;
> -
> - width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
> - height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
> -
> - mbpf = NUM_MBS_PER_FRAME(height, width);
> - mbs_per_second = mbpf * fps;
> -
> - fw_cycles = fps * caps->mb_cycles_fw;
> - fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
> -
> - vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
> - /* 21 / 20 is minimum overhead factor */
> - vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
> -
> - /* 1.059 is multi-pipe overhead */
> - if (inst->fw_caps[PIPE].value > 1)
> - vpp_cycles += div_u64(vpp_cycles * 59, 1000);
> -
> - vsp_cycles = fps * data_size * 8;
> - vsp_cycles = div_u64(vsp_cycles, 2);
> - /* VSP FW overhead 1.05 */
> - vsp_cycles = div_u64(vsp_cycles * 21, 20);
> -
> - if (inst->fw_caps[STAGE].value == STAGE_1)
> - vsp_cycles = vsp_cycles * 3;
> -
> - return max3(vpp_cycles, vsp_cycles, fw_cycles);
> -}
> -
> const struct vpu_ops iris_vpu3_ops = {
> .power_off_hw = iris_vpu3_power_off_hardware,
> .power_on_hw = iris_vpu_power_on_hw,
> .power_off_controller = iris_vpu_power_off_controller,
> .power_on_controller = iris_vpu_power_on_controller,
> - .calc_freq = iris_vpu3x_calculate_frequency,
> + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
> };
>
> const struct vpu_ops iris_vpu33_ops = {
> @@ -424,14 +277,14 @@ const struct vpu_ops iris_vpu33_ops = {
> .power_on_hw = iris_vpu_power_on_hw,
> .power_off_controller = iris_vpu33_power_off_controller,
> .power_on_controller = iris_vpu_power_on_controller,
> - .calc_freq = iris_vpu3x_calculate_frequency,
> + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
> };
>
> const struct vpu_ops iris_vpu35_ops = {
> .power_off_hw = iris_vpu35_power_off_hw,
> .power_on_hw = iris_vpu35_power_on_hw,
> - .power_off_controller = iris_vpu35_power_off_controller,
> - .power_on_controller = iris_vpu35_power_on_controller,
> - .program_bootup_registers = iris_vpu35_program_bootup_registers,
> - .calc_freq = iris_vpu3x_calculate_frequency,
> + .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
> + .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
> + .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
> + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
> };
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index a7b1fb8173e02d22e6f2af4ea170738c6408f65b..dd0990d143a624d83e241d9970297ce1abe37f74 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -8,6 +8,7 @@
> #include <linux/reset.h>
>
> #include "iris_core.h"
> +#include "iris_instance.h"
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> @@ -48,6 +49,10 @@
>
> #define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
>
> +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
> +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL (AON_BASE_OFFS + 0x2C)
> +#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS (AON_BASE_OFFS + 0x30)
> +
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> u32 mask_val;
> @@ -309,6 +314,144 @@ int iris_vpu_power_on_hw(struct iris_core *core)
> return ret;
> }
>
> +int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
> +{
> + u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
> + bool handshake_done, handshake_busy;
> + u32 count = 0, val = 0;
> + int ret;
> +
> + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
> +
> + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> +
> + ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
> + val, val & BIT(0), 200, 2000);
> + if (ret)
> + goto disable_power;
> +
> + writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> +
> + /* Retry up to 1000 times as recommended by hardware documentation */
> + do {
> + /* set MNoC to low power */
> + writel(REQ_POWER_DOWN_PREP, core->reg_base +
> + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> + usleep_range(10, 20);
> + val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);
> +
> + handshake_done = val & NOC_LPI_STATUS_DONE;
> + handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);
> +
> + if (handshake_done || !handshake_busy)
> + break;
> +
> + writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> + usleep_range(10, 20);
> +
> + } while (++count < 1000);
> +
> + if (!handshake_done && handshake_busy)
> + dev_err(core->dev, "LPI handshake timeout\n");
> +
> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
> + val, val & BIT(0), 200, 2000);
> + if (ret)
> + goto disable_power;
> +
> + writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> +
> + writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
> +
> + readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
> + val, val == 0, 200, 2000);
> +
> +disable_power:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> +
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
> +
> + return 0;
> +}
> +
> +int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
> +{
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
> + if (ret)
> + goto err_disable_axi1_clk;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
> + if (ret)
> + goto err_disable_ctrl_free_clk;
> +
> + return 0;
> +
> +err_disable_ctrl_free_clk:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> +err_disable_axi1_clk:
> + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
> +void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core)
> +{
> + writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
> +}
> +
> +u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size)
> +{
> + struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> + struct v4l2_format *inp_f = inst->fmt_src;
> + u32 height, width, mbs_per_second, mbpf;
> + u64 fw_cycles, fw_vpp_cycles;
> + u64 vsp_cycles, vpp_cycles;
> + u32 fps = DEFAULT_FPS;
> +
> + width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
> + height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
> +
> + mbpf = NUM_MBS_PER_FRAME(height, width);
> + mbs_per_second = mbpf * fps;
> +
> + fw_cycles = fps * caps->mb_cycles_fw;
> + fw_vpp_cycles = fps * caps->mb_cycles_fw_vpp;
> +
> + vpp_cycles = mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->fw_caps[PIPE].value);
> + /* 21 / 20 is minimum overhead factor */
> + vpp_cycles += max(div_u64(vpp_cycles, 20), fw_vpp_cycles);
> +
> + /* 1.059 is multi-pipe overhead */
> + if (inst->fw_caps[PIPE].value > 1)
> + vpp_cycles += div_u64(vpp_cycles * 59, 1000);
> +
> + vsp_cycles = fps * data_size * 8;
> + vsp_cycles = div_u64(vsp_cycles, 2);
> + /* VSP FW overhead 1.05 */
> + vsp_cycles = div_u64(vsp_cycles * 21, 20);
> +
> + if (inst->fw_caps[STAGE].value == STAGE_1)
> + vsp_cycles = vsp_cycles * 3;
> +
> + return max3(vpp_cycles, vsp_cycles, fw_cycles);
> +}
> +
> int iris_vpu_power_on(struct iris_core *core)
> {
> u32 freq;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> index d636e287457adf0c44540af5c85cfa69decbca8b..7cf4304604cca590544a938c7e811c202cea3d93 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> @@ -33,5 +33,9 @@ int iris_vpu_power_on(struct iris_core *core);
> int iris_vpu_power_off_controller(struct iris_core *core);
> void iris_vpu_power_off_hw(struct iris_core *core);
> void iris_vpu_power_off(struct iris_core *core);
> +int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core);
> +int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core);
> +void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core);
> +u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size);
>
> #endif
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs
2025-10-17 14:16 ` [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs Vikash Garodia
@ 2025-10-21 23:35 ` Bryan O'Donoghue
0 siblings, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:35 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Bryan O'Donoghue
On 17/10/2025 15:16, Vikash Garodia wrote:
> vpu4 needs an additional configuration with respect to CP regions. Make
> the CP configuration as array such that the multiple configuration can be
> managed per platform.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_firmware.c | 23 ++++++++++++---------
> .../platform/qcom/iris/iris_platform_common.h | 3 ++-
> .../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++++++++++--------
> .../platform/qcom/iris/iris_platform_sm8250.c | 15 ++++++++------
> 4 files changed, 39 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
> index 9ab499fad946446a87036720f49c9c8d311f3060..9186e0144dc0df4045c9995adc5fc93993cc3fba 100644
> --- a/drivers/media/platform/qcom/iris/iris_firmware.c
> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c
> @@ -70,9 +70,9 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
>
> int iris_fw_load(struct iris_core *core)
> {
> - struct tz_cp_config *cp_config = core->iris_platform_data->tz_cp_config_data;
> + const struct tz_cp_config *cp_config;
> const char *fwpath = NULL;
> - int ret;
> + int i, ret;
>
> ret = of_property_read_string_index(core->dev->of_node, "firmware-name", 0,
> &fwpath);
> @@ -91,14 +91,17 @@ int iris_fw_load(struct iris_core *core)
> return ret;
> }
>
> - ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> - cp_config->cp_size,
> - cp_config->cp_nonpixel_start,
> - cp_config->cp_nonpixel_size);
> - if (ret) {
> - dev_err(core->dev, "protect memory failed\n");
> - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> - return ret;
> + for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
> + cp_config = &core->iris_platform_data->tz_cp_config_data[i];
> + ret = qcom_scm_mem_protect_video_var(cp_config->cp_start,
> + cp_config->cp_size,
> + cp_config->cp_nonpixel_start,
> + cp_config->cp_nonpixel_size);
> + if (ret) {
> + dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
> + qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> + return ret;
> + }
> }
>
> return ret;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index df03de08c44839c1b6c137874eb7273c638d5f2c..ae49e95ba2252fc1442f7c81d8010dbfd86da0da 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -220,7 +220,8 @@ struct iris_platform_data {
> u32 inst_fw_caps_dec_size;
> struct platform_inst_fw_cap *inst_fw_caps_enc;
> u32 inst_fw_caps_enc_size;
> - struct tz_cp_config *tz_cp_config_data;
> + const struct tz_cp_config *tz_cp_config_data;
> + u32 tz_cp_config_data_size;
> u32 core_arch;
> u32 hw_response_timeout;
> struct ubwc_config_data *ubwc_config;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index fea800811a389a58388175c733ad31c4d9c636b0..00c6b9021b98aac80612b1bb9734c8dac8146bd9 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -648,11 +648,13 @@ static struct ubwc_config_data ubwc_config_sm8550 = {
> .bank_spreading = 1,
> };
>
> -static struct tz_cp_config tz_cp_config_sm8550 = {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> +static const struct tz_cp_config tz_cp_config_sm8550[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> };
>
> static const u32 sm8550_vdec_input_config_params_default[] = {
> @@ -771,7 +773,8 @@ struct iris_platform_data sm8550_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -864,7 +867,8 @@ struct iris_platform_data sm8650_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -947,7 +951,8 @@ struct iris_platform_data sm8750_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> @@ -1035,7 +1040,8 @@ struct iris_platform_data qcs8300_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> .inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8550,
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> .core_arch = VIDEO_ARCH_LX,
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .ubwc_config = &ubwc_config_sm8550,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 1b1b6aa751106ee0b0bc71bb0df2e78340190e66..8927c3ff59dab59c7d2cbcd92550f9ee3a2b5c1e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -278,11 +278,13 @@ static const char * const sm8250_opp_clk_table[] = {
> NULL,
> };
>
> -static struct tz_cp_config tz_cp_config_sm8250 = {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> +static const struct tz_cp_config tz_cp_config_sm8250[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> };
>
> static const u32 sm8250_vdec_input_config_param_default[] = {
> @@ -348,7 +350,8 @@ struct iris_platform_data sm8250_data = {
> .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
> .inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
> .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
> - .tz_cp_config_data = &tz_cp_config_sm8250,
> + .tz_cp_config_data = tz_cp_config_sm8250,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
> .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> .num_vpp_pipe = 4,
> .max_session_count = 16,
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 8/8] media: iris: Add platform data for kaanapali
2025-10-17 14:16 ` [PATCH v2 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
@ 2025-10-21 23:39 ` Bryan O'Donoghue
2025-10-22 5:46 ` Vikash Garodia
2025-10-22 15:20 ` Bryan O'Donoghue
1 sibling, 1 reply; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-21 23:39 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> + .fwname = "qcom/vpu/vpu40_p2_s7.mbn",
Dmitry pays more attention to this stuff than I have but, is this a
released firmware ?
If not, are we sure this _will_ be the correct name that hits
linux-firmware upstream ?
---
bod
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4
2025-10-21 23:25 ` Bryan O'Donoghue
@ 2025-10-22 5:44 ` Vikash Garodia
0 siblings, 0 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-22 5:44 UTC (permalink / raw)
To: Bryan O'Donoghue, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/22/2025 4:55 AM, Bryan O'Donoghue wrote:
> On 17/10/2025 15:16, Vikash Garodia wrote:
>> Introduces vp4 buffer size calculation for both encoder and decoder.
>> Reuse the buffer size calculation which are common, while adding the
>> vpu4 ones separately.
>>
>> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
>> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 345 +++++++++++++++++++++
>> drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 15 +
>> 2 files changed, 360 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
>> b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
>> index
>> 4463be05ce165adef6b152eb0c155d2e6a7b3c36..8cc52d7aba3ffb968191519c1a1a10e326403205 100644
>> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
>> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
>> @@ -1408,6 +1408,307 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
>> return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
>> }
>>
>> +static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
>> +{
>> + u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
>> + u32 dpb_opb = 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT);
>> + u32 num_luma_chrome_plane = 2;
>> +
>> + return dpb_opb = num_luma_chrome_plane * ALIGN(dpb_opb, DMA_ALIGNMENT);
>
> return thing = someother-thing.
>
> You must mean
>
> return (num_luma_chrome_plane * ALIGN(dpb_opb, DMA_ALIGNMENT));
Ack
>
>> +}
>> +
>> +static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32
>> num_vpp_pipes)
>> +{
>> + u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp,
>> num_lcu_per_pipe;
>> + u32 lcu_size = 64, fe_top_ctrl_line_numbers = 3,
>> fe_top_data_luma_line_numbers = 2,
>> + fe_top_data_chroma_line_numbers = 3, fe_lft_ctrl_line_numbers = 4,
>> + fe_lft_db_data_line_numbers = 2, fe_lft_lr_data_line_numbers = 4;
>
> You can reduce this very long variable list to macro constants.
>
> For example fe_lft_db_data_line_numbers doesn't vary so it shouldn't be a variable.
>
Ack
>> +
>> + vp9_top_lb = ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height),
>> DMA_ALIGNMENT);
>> + vp9_top_lb += ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height),
>> DMA_ALIGNMENT);
>> + vp9_top_lb += max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES) *
>> + MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE,
>> + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) *
>> + MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE,
>> + DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) *
>> + MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE);
>> + vp9_top_lb = ALIGN(vp9_top_lb, DMA_ALIGNMENT);
>> + vp9_top_lb += ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)),
>> + DMA_ALIGNMENT) * fe_top_ctrl_line_numbers;
>> + vp9_top_lb += ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_size),
>> + DMA_ALIGNMENT) * (fe_top_data_luma_line_numbers +
>> + fe_top_data_chroma_line_numbers);
>> +
>> + num_lcu_per_pipe = (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipes) +
>> + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes);
>> + vp9_fe_left_lb = ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) *
>> + fe_lft_ctrl_line_numbers;
>> + vp9_fe_left_lb += ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe),
>> DMA_ALIGNMENT) *
>> + fe_lft_db_data_line_numbers) +
>> + ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) +
>> + ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) +
>> + (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) *
>> + fe_lft_lr_data_line_numbers));
>> + vp9_fe_left_lb = vp9_fe_left_lb * num_vpp_pipes;
>> +
>> + vp9_se_left_lb = ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height),
>> + DMA_ALIGNMENT);
>> + dpb_opb = size_dpb_opb(frame_height, lcu_size);
>> + vp9d_qp = ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
>> +
>> + return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) +
>> + (dpb_opb * num_vpp_pipes) + vp9d_qp;
>> +}
>> +
>> +static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32
>> _yuv_bufcount_min,
>> + bool is_opb, u32 num_vpp_pipes)
>> +{
>> + u32 lb_size = hfi_vpu4x_vp9d_lb_size(frame_width, frame_height,
>> num_vpp_pipes);
>> + u32 dpb_obp_size = 0, lcu_size = 64;
>> +
>> + if (is_opb)
>> + dpb_obp_size = size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes;
>> +
>> + return lb_size + dpb_obp_size;
>> +}
>> +
>> +static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
>> +{
>> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
>> + u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
>> + struct v4l2_format *f = inst->fmt_src;
>> + u32 height = f->fmt.pix_mp.height;
>> + u32 width = f->fmt.pix_mp.width;
>> + bool is_opb = false;
>> +
>> + if (iris_split_mode_enabled(inst))
>> + is_opb = true;
>> +
>> + if (inst->codec == V4L2_PIX_FMT_H264)
>> + return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
>> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
>> + return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
>> + else if (inst->codec == V4L2_PIX_FMT_VP9)
>> + return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
>> + num_vpp_pipes);
>> +
>> + return 0;
>> +}
>> +
>> +static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled)
>> +{
>> + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INFO *
>> + H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) +
>> (NUM_HW_PIC_BUF *
>> + (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) +
>> + rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT);
>> +}
>> +
>> +static u32 hfi_vpu4x_buffer_persist_vp9d(void)
>> +{
>> + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE,
>> DMA_ALIGNMENT) +
>> + (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) +
>> + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) +
>> + ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) +
>> + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) +
>> + ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X,
>> DMA_ALIGNMENT) +
>> + HDR10_HIST_EXTRADATA_SIZE;
>> +}
>> +
>> +static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
>> +{
>> + if (inst->codec == V4L2_PIX_FMT_H264)
>> + return hfi_buffer_persist_h264d();
>> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
>> + return hfi_vpu4x_buffer_persist_h265d(0);
>> + else if (inst->codec == V4L2_PIX_FMT_VP9)
>> + return hfi_vpu4x_buffer_persist_vp9d();
>> +
>> + return 0;
>> +}
>> +
>> +static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc,
>> + u32 frame_width_coded, u32 frame_height_coded)
>> +{
>> + u32 se_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
>> + u32 se_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
>> + ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
>> + BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
>> + ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
>> + BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
>> +
>> + se_llb_size = ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES);
>> +
>> + if (num_vpp_pipes_enc > 1)
>> + se_llb_size = ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES,
>> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
>> +
>> + return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT);
>> +}
>> +
>> +static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in_lcus,
>> + u32 frame_height_coded, u32 frame_width_coded)
>> +{
>> + u32 num_pixel_10_bit = 3, num_pixel_8_bit = 2, num_pixel_te_llb = 3;
>> + u32 te_llb_col_rc_size = ALIGN(32 * width_in_lcus / num_vpp_pipes_enc,
>> + DMA_ALIGNMENT) * num_vpp_pipes_enc;
>> + u32 te_tlb_recon_data_size = ALIGN((is_ten_bit ? num_pixel_10_bit :
>> num_pixel_8_bit) *
>> + frame_width_coded, DMA_ALIGNMENT);
>> + u32 te_llb_recon_data_size = ((1 + is_ten_bit) * num_pixel_te_llb *
>> frame_height_coded +
>> + num_vpp_pipes_enc - 1) / num_vpp_pipes_enc;
>> + te_llb_recon_data_size = ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) *
>> num_vpp_pipes_enc;
>> +
>> + return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size +
>> te_tlb_recon_data_size,
>> + DMA_ALIGNMENT);
>> +}
>> +
>> +static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit)
>> +{
>> + u32 num_pixels_fe_tlb_10_bit = 128, num_pixels_fe_tlb_8_bit = 64;
>> +
>> + return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) :
>> + (size_per_lcu * num_pixels_fe_tlb_8_bit);
>> +}
>> +
>> +static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc,
>> + u32 frame_height_coded, u32 frame_width_coded)
>> +{
>> + u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width,
>> + fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size,
>> + fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size,
>> + fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size,
>> + fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size,
>> + fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu;
>> + u32 fe_sdc_data_per_block = 16, se_ctrl_data_per_block = 2020;
>
> Again you can reduce this - at least a little bit
>
> fe_sdc_data_per_block
> se_ctrl_data_per_block
>
> are const
Ack
>
>> +
>> + log2_lcu_size = (standard == HFI_CODEC_ENCODE_HEVC) ? 5 : 4;
>> + num_cu_in_height_pipe = ((frame_height_coded >> log2_lcu_size) +
>> num_vpp_pipes_enc - 1) /
>> + num_vpp_pipes_enc;
>> + num_cu_in_width = frame_width_coded >> log2_lcu_size;
>> +
>> + size_per_lcu = 2;
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
>> + fb_llb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) *
>> num_cu_in_height_pipe;
>> + fb_llb_db_ctrl_size = ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) *
>> num_vpp_pipes_enc;
>> +
>> + size_per_lcu = (1 << (log2_lcu_size - 3));
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
>> + fb_llb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) *
>> num_cu_in_height_pipe;
>> + fb_llb_db_luma_size = ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) *
>> num_vpp_pipes_enc;
>> +
>> + size_per_lcu = ((1 << (log2_lcu_size - 4)) * 2);
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
>> + fb_llb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) *
>> num_cu_in_height_pipe;
>> + fb_llb_db_chroma_size = ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) *
>> num_vpp_pipes_enc;
>> +
>> + size_per_lcu = 1;
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
>> + fb_tlb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
>> + fb_llb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) *
>> num_cu_in_height_pipe;
>> + fb_llb_sao_ctrl_size = fb_llb_sao_ctrl_size * num_vpp_pipes_enc;
>> + fb_tlb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
>> +
>> + size_per_lcu = ((1 << (log2_lcu_size - 3)) + 1);
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
>> + fb_tlb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
>> +
>> + size_per_lcu = (2 * ((1 << (log2_lcu_size - 4)) + 1));
>> + fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
>> + fb_tlb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
>> +
>> + fb_llb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
>> + fb_llb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
>> + fb_tlb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES;
>> + fb_tlb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES;
>> + fb_lb_top_sdc_size = ALIGN((fe_sdc_data_per_block * (frame_width_coded >>
>> 5)),
>> + DMA_ALIGNMENT);
>> + fb_lb_se_ctrl_size = ALIGN((se_ctrl_data_per_block * (frame_width_coded
>> >> 5)),
>> + DMA_ALIGNMENT);
>
> On the one hand lots of variables.
>
> On the other hand I think the code is more readable with assigned names instead
> of a big morass of return ALIGN(stuff) + ALIGN(other stuff).
Good to know its better now interms of readability.
>
> Anyway I think you can reduce this enormomous variable list by at lest two.
>
> u32 fe_sdc_data_per_block = 16, se_ctrl_data_per_block = 2020;
> ->
> #define FE_SDC_DATA_PER_BLOCK 16
> #define SE_CTRL_DATA_PER_BLOCK 2020
>
Ack
Regards,
Vikash
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 8/8] media: iris: Add platform data for kaanapali
2025-10-21 23:39 ` Bryan O'Donoghue
@ 2025-10-22 5:46 ` Vikash Garodia
0 siblings, 0 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-10-22 5:46 UTC (permalink / raw)
To: Bryan O'Donoghue, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/22/2025 5:09 AM, Bryan O'Donoghue wrote:
> On 17/10/2025 15:16, Vikash Garodia wrote:
>> + .fwname = "qcom/vpu/vpu40_p2_s7.mbn",
>
> Dmitry pays more attention to this stuff than I have but, is this a released
> firmware ?
>
> If not, are we sure this _will_ be the correct name that hits linux-firmware
> upstream ?
Yes, the naming was discussed and the bins are accepted in linux-firmware
Regards,
Vikash
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-21 21:07 ` Vikash Garodia
@ 2025-10-22 6:04 ` Krzysztof Kozlowski
2025-10-22 9:37 ` Dmitry Baryshkov
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-22 6:04 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 21/10/2025 23:07, Vikash Garodia wrote:
>
> On 10/22/2025 12:45 AM, Krzysztof Kozlowski wrote:
>> On 21/10/2025 20:55, Vikash Garodia wrote:
>>>
>>> On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
>>>> On 17/10/2025 16:16, Vikash Garodia wrote:
>>>>> + clock-names:
>>>>> + items:
>>>>> + - const: iface
>>>>> + - const: core
>>>>> + - const: vcodec0_core
>>>>> + - const: iface1
>>>>> + - const: core_freerun
>>>>> + - const: vcodec0_core_freerun
>>>>> + - const: vcodec_bse
>>>>> + - const: vcodec_vpp0
>>>>> + - const: vcodec_vpp1
>>>>> + - const: vcodec_apv
>>>>> +
>>>>> + dma-coherent: true
>>>>> +
>>>>> + firmware-name:
>>>>> + maxItems: 1
>>>>> +
>>>>> + interconnects:
>>>>> + maxItems: 2
>>>>> +
>>>>> + interconnect-names:
>>>>> + items:
>>>>> + - const: cpu-cfg
>>>>> + - const: video-mem
>>>>> +
>>>>> + interrupts:
>>>>> + maxItems: 1
>>>>> +
>>>>> + iommus:
>>>>> + minItems: 3
>>>>> + maxItems: 8
>>>>
>>>> I don't understand why this is flexible. Make it fixed size and anyway -
>>>> list the items.
>>>
>>> kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
>>> EL2 mode can list all of them, while boards running in EL1 can have only non
>>> secure stream IDs. Min have the list of stream ids which can be enabled for all
>>> type of boards, while max is for boards which can list all in HLOS given kernel
>>> is in EL2 mode.
>>>
>>> Below crash would be seen if boards running kernel in EL1 mode lists the secure
>>> ones.
>>
>>
>> That has to be explained somewhere, e.g. comment,
>
> Sure, will add a description for iommus property explaining the same.
>
> and still we need then
>> EL2 DTS in the kernel. I did not see such so far, but maybe I missed it
>> - can you link it?
>>
>
> EL2 DTS for kaanapali is not yet posted to handle secure SIDs. While it is in
> development, describing the secure stream-ids would ensure to cover all the
> hardware generated IDs.
Then maybe this binding should wait till we see entire picture of hardware.
>
>>>
>>> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
>>> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
>>> [ 1.361168] sp : ffff80008005b8f0
>>> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
>>> ....
>>> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
>>> [ 1.361198] Call trace:
>>> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
>>> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
>>> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>>>
>>> Could you please suggest on listing the iommu items ? I did not find the
>>> relevant references in other bindings where flexible iommus is being listed.
>>
>>
>> Just like every other list property - clocks, resets, power-domains.
>>
> something like
>
> iommu-names:
> items:
> - const: 0x1943
> - const: 0x1940
> ...
>
> given that one of vpu sub hardware generates multiple SIDs, if we go with sub
> hardware name in the list, the names would be repeated.
No, we describe items, what are their meaning and purpose. In case of
clock you say what sort of clock input is that. In case of here, you
have IOMMUs for different purpose, you say which purpose is that.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform
2025-10-17 14:36 ` [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Nicolas Dufresne
@ 2025-10-22 6:07 ` Vikash Garodia
2025-11-10 7:45 ` Vikash Garodia
0 siblings, 1 reply; 32+ messages in thread
From: Vikash Garodia @ 2025-10-22 6:07 UTC (permalink / raw)
To: Nicolas Dufresne, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Bryan O'Donoghue
Hello Nicolas,
On 10/17/2025 8:06 PM, Nicolas Dufresne wrote:
> Hi Vikash,
>
> Le vendredi 17 octobre 2025 à 19:46 +0530, Vikash Garodia a
>> [ 350.438406] qcom-iris 2000000.video-codec: invalid plane
>> [ 350.447079] qcom-iris 2000000.video-codec: invalid plane
>> [ 350.458821] qcom-iris 2000000.video-codec: invalid plane
>> [ 350.465860] qcom-iris 2000000.video-codec: invalid plane
>
> Just a highlight, the driver should only print stuff on default log level if
> something is malfunctioning. uAPI miss-use should only be trace on loglevel
> manually enabled by the developers. Mind fixing this up while at it ? Hopefully
> this will be obvious to you next time you encounter it.
Agree, this specific log should not be part of default execution and more so
when this is not malfunctioning. I would remove this log as i see it can be dropped.
Regards,
Vikash
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-21 21:07 ` Vikash Garodia
2025-10-22 6:04 ` Krzysztof Kozlowski
@ 2025-10-22 9:37 ` Dmitry Baryshkov
2025-10-22 14:51 ` Bryan O'Donoghue
1 sibling, 1 reply; 32+ messages in thread
From: Dmitry Baryshkov @ 2025-10-22 9:37 UTC (permalink / raw)
To: Vikash Garodia
Cc: Krzysztof Kozlowski, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Konrad Dybcio,
linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On Wed, Oct 22, 2025 at 02:37:59AM +0530, Vikash Garodia wrote:
>
> On 10/22/2025 12:45 AM, Krzysztof Kozlowski wrote:
> > On 21/10/2025 20:55, Vikash Garodia wrote:
> >>
> >> On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
> >>> On 17/10/2025 16:16, Vikash Garodia wrote:
> >>>> + clock-names:
> >>>> + items:
> >>>> + - const: iface
> >>>> + - const: core
> >>>> + - const: vcodec0_core
> >>>> + - const: iface1
> >>>> + - const: core_freerun
> >>>> + - const: vcodec0_core_freerun
> >>>> + - const: vcodec_bse
> >>>> + - const: vcodec_vpp0
> >>>> + - const: vcodec_vpp1
> >>>> + - const: vcodec_apv
> >>>> +
> >>>> + dma-coherent: true
> >>>> +
> >>>> + firmware-name:
> >>>> + maxItems: 1
> >>>> +
> >>>> + interconnects:
> >>>> + maxItems: 2
> >>>> +
> >>>> + interconnect-names:
> >>>> + items:
> >>>> + - const: cpu-cfg
> >>>> + - const: video-mem
> >>>> +
> >>>> + interrupts:
> >>>> + maxItems: 1
> >>>> +
> >>>> + iommus:
> >>>> + minItems: 3
> >>>> + maxItems: 8
> >>>
> >>> I don't understand why this is flexible. Make it fixed size and anyway -
> >>> list the items.
> >>
> >> kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
> >> EL2 mode can list all of them, while boards running in EL1 can have only non
> >> secure stream IDs. Min have the list of stream ids which can be enabled for all
> >> type of boards, while max is for boards which can list all in HLOS given kernel
> >> is in EL2 mode.
> >>
> >> Below crash would be seen if boards running kernel in EL1 mode lists the secure
> >> ones.
> >
> >
> > That has to be explained somewhere, e.g. comment,
>
> Sure, will add a description for iommus property explaining the same.
>
> and still we need then
> > EL2 DTS in the kernel. I did not see such so far, but maybe I missed it
> > - can you link it?
> >
>
> EL2 DTS for kaanapali is not yet posted to handle secure SIDs. While it is in
> development, describing the secure stream-ids would ensure to cover all the
> hardware generated IDs.
EL2 is a slightly different topic, it most likely requires additional
changes, etc. I'd suggest focusing on a normal usecase first and getting
the EL2 sorted out separately.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-22 9:37 ` Dmitry Baryshkov
@ 2025-10-22 14:51 ` Bryan O'Donoghue
0 siblings, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-22 14:51 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia
Cc: Krzysztof Kozlowski, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Konrad Dybcio, linux-arm-msm,
linux-media, devicetree, linux-kernel, Vishnu Reddy
On 22/10/2025 10:37, Dmitry Baryshkov wrote:
>> EL2 DTS for kaanapali is not yet posted to handle secure SIDs. While it is in
>> development, describing the secure stream-ids would ensure to cover all the
>> hardware generated IDs.
> EL2 is a slightly different topic, it most likely requires additional
> changes, etc. I'd suggest focusing on a normal usecase first and getting
> the EL2 sorted out separately.
Is the conversion to EL2 only for compute then, Kanaapali is a gunyah
system - Linux running @ EL1 here ?
---
bod
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 8/8] media: iris: Add platform data for kaanapali
2025-10-17 14:16 ` [PATCH v2 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
2025-10-21 23:39 ` Bryan O'Donoghue
@ 2025-10-22 15:20 ` Bryan O'Donoghue
1 sibling, 0 replies; 32+ messages in thread
From: Bryan O'Donoghue @ 2025-10-22 15:20 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 17/10/2025 15:16, Vikash Garodia wrote:
> Add support for the kaanapali platform by re-using the SM8550
> definitions and using the vpu4 ops.
> Move the configurations that differs in a per-SoC platform
> header, that will contain SoC specific data.
>
> Co-developed-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vishnu Reddy <quic_bvisredd@quicinc.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 86 ++++++++++++++++++++++
> .../platform/qcom/iris/iris_platform_kaanapali.h | 63 ++++++++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 4 files changed, 154 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index d6d4a9fdfc189797f903dfeb56d931741b405ee2..f77bad531f067f59b48c3e4caa40a463d454c47e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -41,6 +41,7 @@ enum pipe_type {
> PIPE_4 = 4,
> };
>
> +extern struct iris_platform_data kaanapali_data;
> extern struct iris_platform_data qcs8300_data;
> extern struct iris_platform_data sm8250_data;
> extern struct iris_platform_data sm8550_data;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 00c6b9021b98aac80612b1bb9734c8dac8146bd9..104c24fd47770dff770a5230cf957d78c89b01f7 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -12,6 +12,7 @@
> #include "iris_vpu_buffer.h"
> #include "iris_vpu_common.h"
>
> +#include "iris_platform_kaanapali.h"
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
> @@ -744,6 +745,91 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
> BUF_SCRATCH_2,
> };
>
> +struct iris_platform_data kaanapali_data = {
> + .get_instance = iris_hfi_gen2_get_instance,
> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> + .get_vpu_buffer_size = iris_vpu4x_buf_size,
> + .vpu_ops = &iris_vpu4x_ops,
> + .set_preset_registers = iris_set_sm8550_preset_registers,
> + .icc_tbl = sm8550_icc_table,
> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> + .clk_rst_tbl = kaanapali_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(kaanapali_clk_reset_table),
> + .bw_tbl_dec = sm8550_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> + .pmdomain_tbl = kaanapali_pmdomain_table,
> + .pmdomain_tbl_size = ARRAY_SIZE(kaanapali_pmdomain_table),
> + .opp_pd_tbl = sm8550_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> + .clk_tbl = kaanapali_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(kaanapali_clk_table),
> + .opp_clk_tbl = kaanapali_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu40_p2_s7.mbn",
> + .pas_id = IRIS_PAS_ID,
> + .inst_caps = &platform_inst_cap_sm8550,
> + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> + .tz_cp_config_data = tz_cp_config_kaanapali,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_kaanapali),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .ubwc_config = &ubwc_config_sm8550,
> + .num_vpp_pipe = 2,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K * 2,
> + .max_core_mbps = ((8192 * 4352) / 256) * 60,
> + .dec_input_config_params_default =
> + sm8550_vdec_input_config_params_default,
> + .dec_input_config_params_default_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_params_default),
> + .dec_input_config_params_hevc =
> + sm8550_vdec_input_config_param_hevc,
> + .dec_input_config_params_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
> + .dec_input_config_params_vp9 =
> + sm8550_vdec_input_config_param_vp9,
> + .dec_input_config_params_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
> + .dec_output_config_params =
> + sm8550_vdec_output_config_params,
> + .dec_output_config_params_size =
> + ARRAY_SIZE(sm8550_vdec_output_config_params),
> +
> + .enc_input_config_params =
> + sm8550_venc_input_config_params,
> + .enc_input_config_params_size =
> + ARRAY_SIZE(sm8550_venc_input_config_params),
> + .enc_output_config_params =
> + sm8550_venc_output_config_params,
> + .enc_output_config_params_size =
> + ARRAY_SIZE(sm8550_venc_output_config_params),
> +
> + .dec_input_prop = sm8550_vdec_subscribe_input_properties,
> + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
> + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
> + .dec_output_prop_avc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
> + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
> + .dec_output_prop_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
> + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
> + .dec_output_prop_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
> +
> + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
> + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
> +
> + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> +};
> +
> struct iris_platform_data sm8550_data = {
> .get_instance = iris_hfi_gen2_get_instance,
> .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..247fb9d7cb632d2e9a1e9832d087cb03ac9b7cf3
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_kaanapali.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef __IRIS_PLATFORM_KAANAPALI_H__
> +#define __IRIS_PLATFORM_KAANAPALI_H__
> +
> +#define VIDEO_REGION_VM0_SECURE_NP_ID 1
> +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
> +
> +static const char *const kaanapali_clk_reset_table[] = {
> + "bus0",
> + "bus1",
> + "core_freerun_reset",
> + "vcodec0_core_freerun_reset",
> +};
> +
> +static const char *const kaanapali_pmdomain_table[] = {
> + "venus",
> + "vcodec0",
> + "vpp0",
> + "vpp1",
> + "apv",
> +};
> +
> +static const struct platform_clk_data kaanapali_clk_table[] = {
> + { IRIS_AXI_CLK, "iface" },
> + { IRIS_CTRL_CLK, "core" },
> + { IRIS_HW_CLK, "vcodec0_core" },
> + { IRIS_AXI1_CLK, "iface1" },
> + { IRIS_CTRL_FREERUN_CLK, "core_freerun" },
> + { IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
> + { IRIS_BSE_HW_CLK, "vcodec_bse" },
> + { IRIS_VPP0_HW_CLK, "vcodec_vpp0" },
> + { IRIS_VPP1_HW_CLK, "vcodec_vpp1" },
> + { IRIS_APV_HW_CLK, "vcodec_apv" },
> +};
> +
> +static const char *const kaanapali_opp_clk_table[] = {
> + "vcodec0_core",
> + "vcodec_apv",
> + "vcodec_bse",
> + "core",
> + NULL,
> +};
> +
> +static struct tz_cp_config tz_cp_config_kaanapali[] = {
> + {
> + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
> + .cp_size = 0,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> + {
> + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
> + .cp_size = 0,
> + .cp_nonpixel_start = 0x25800000,
> + .cp_nonpixel_size = 0xda400000,
> + },
> +};
> +
> +#endif /* __IRIS_PLATFORM_KAANAPALI_H__ */
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index ad82a62f8b923d818ffe77c131d7eb6da8c34002..a0902f3aaa1ca6021cfd414787da747a6dda1010 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = {
> };
>
> static const struct of_device_id iris_dt_match[] = {
> + {
> + .compatible = "qcom,kaanapali-iris",
> + .data = &kaanapali_data,
> + },
> {
> .compatible = "qcom,qcs8300-iris",
> .data = &qcs8300_data,
>
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-21 18:55 ` Vikash Garodia
2025-10-21 19:15 ` Krzysztof Kozlowski
@ 2025-10-22 15:36 ` Konrad Dybcio
2025-10-22 16:28 ` Krzysztof Kozlowski
1 sibling, 1 reply; 32+ messages in thread
From: Konrad Dybcio @ 2025-10-22 15:36 UTC (permalink / raw)
To: Vikash Garodia, Krzysztof Kozlowski, Dikshita Agarwal,
Abhinav Kumar, Bryan O'Donoghue, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/21/25 8:55 PM, Vikash Garodia wrote:
>
> On 10/18/2025 9:28 PM, Krzysztof Kozlowski wrote:
>> On 17/10/2025 16:16, Vikash Garodia wrote:
>>> + clock-names:
>>> + items:
>>> + - const: iface
>>> + - const: core
>>> + - const: vcodec0_core
>>> + - const: iface1
>>> + - const: core_freerun
>>> + - const: vcodec0_core_freerun
>>> + - const: vcodec_bse
>>> + - const: vcodec_vpp0
>>> + - const: vcodec_vpp1
>>> + - const: vcodec_apv
>>> +
>>> + dma-coherent: true
>>> +
>>> + firmware-name:
>>> + maxItems: 1
>>> +
>>> + interconnects:
>>> + maxItems: 2
>>> +
>>> + interconnect-names:
>>> + items:
>>> + - const: cpu-cfg
>>> + - const: video-mem
>>> +
>>> + interrupts:
>>> + maxItems: 1
>>> +
>>> + iommus:
>>> + minItems: 3
>>> + maxItems: 8
>>
>> I don't understand why this is flexible. Make it fixed size and anyway -
>> list the items.
>
> kaanapali vpu generates 8 different stream-ids. Now, boards running kernel in
> EL2 mode can list all of them, while boards running in EL1 can have only non
> secure stream IDs. Min have the list of stream ids which can be enabled for all
> type of boards, while max is for boards which can list all in HLOS given kernel
> is in EL2 mode.
>
> Below crash would be seen if boards running kernel in EL1 mode lists the secure
> ones.
>
> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
> [ 1.361168] sp : ffff80008005b8f0
> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
> ....
> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
> [ 1.361198] Call trace:
> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>
> Could you please suggest on listing the iommu items ? I did not find the
> relevant references in other bindings where flexible iommus is being listed.
Krzysztof would probably like to see what I believe someone else somewhere
sometime suggested in the iommus discussions (sorry it's not possible to
keep track of it all), where the DT can list every possible required iommu
sid, but the driver ensures only the ones that are necessary are utilized.
This will require big changes to the iommu framework though, I'm afraid
>> I already asked this.
>>
>>> +
>>> + memory-region:
>>> + minItems: 1
>>> + maxItems: 2
>>
>> Same comment. I already asked this about iommus.
>
> Same here, there aren't any bindings which lists for flexible memory-region.
> Please suggest if there are any such references.
Similarly, we can define the additional memory region that's necessary
for $reasons and leave it unused in the driver (actually I don't know
why there may be two, but let's assume it's a QTEE/noQTEE detail), because
for the hw to operate, it must be set up by some entity in the system
either way (i.e. the memory is reserved even if it's not done by Linux)
Konrad
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-22 15:36 ` Konrad Dybcio
@ 2025-10-22 16:28 ` Krzysztof Kozlowski
2025-11-06 14:50 ` Vikash Garodia
0 siblings, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-22 16:28 UTC (permalink / raw)
To: Konrad Dybcio, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 22/10/2025 17:36, Konrad Dybcio wrote:
>>
>> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
>> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
>> [ 1.361168] sp : ffff80008005b8f0
>> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
>> ....
>> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
>> [ 1.361198] Call trace:
>> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
>> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
>> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>>
>> Could you please suggest on listing the iommu items ? I did not find the
>> relevant references in other bindings where flexible iommus is being listed.
>
> Krzysztof would probably like to see what I believe someone else somewhere
> sometime suggested in the iommus discussions (sorry it's not possible to
> keep track of it all), where the DT can list every possible required iommu
> sid, but the driver ensures only the ones that are necessary are utilized.
>
> This will require big changes to the iommu framework though, I'm afraid
>
>>> I already asked this.
>>>
>>>> +
>>>> + memory-region:
>>>> + minItems: 1
>>>> + maxItems: 2
>>>
>>> Same comment. I already asked this about iommus.
>>
>> Same here, there aren't any bindings which lists for flexible memory-region.
>> Please suggest if there are any such references.
>
> Similarly, we can define the additional memory region that's necessary
> for $reasons and leave it unused in the driver (actually I don't know
> why there may be two, but let's assume it's a QTEE/noQTEE detail), because
> for the hw to operate, it must be set up by some entity in the system
> either way (i.e. the memory is reserved even if it's not done by Linux)
Another point is pretty obvious: if one claims that
iommus/memory-regions list is flexible - some elements are optional -
then clearly there is a distinction which elements are mandatory and
which are optional. So there is difference between elements of the
array. If there is a difference, they all must be explicitly listed,
like every other list (clocks, resets etc) property. Writing bindings
doc also defines this rule.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
` (8 preceding siblings ...)
2025-10-17 14:36 ` [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Nicolas Dufresne
@ 2025-10-22 17:26 ` Konrad Dybcio
9 siblings, 0 replies; 32+ messages in thread
From: Konrad Dybcio @ 2025-10-22 17:26 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Bryan O'Donoghue
On 10/17/25 4:16 PM, Vikash Garodia wrote:
> Qualcomm kaanapali platform have a newer generation of video IP, iris4
> or vpu4. The hardware have evolved mostly w.r.t higher number of power
> domains as well as multiple clock sources. It has support for new
> codec(apv), when compared to prior generation.
>
> The series describes the binding interfaces of the hardware, buffer
> calculation and power sequence for vpu4, and add the platform data at
> the end.
>
> Please review and share your comments.
>
> Following are the compliance and functional validation reports
>
> v4l2-compliance report, for decoder followed by encoder, including
> streaming tests:
[...]
> Changes in v2:
> - Dropped dependencies from binding (Dmitry).
> - Dropped optional items from binding (Dmitry, Krzysztof, Konrad).
> - Updated binding in sorted order and proper alignment (Krzysztof).
> - Fixed order of newly introduced kaanapali struct (Dmitry, Bryan)
> - Improved readability of buffer size calculation (Bryan)
> - Optimized fuse register read (Konrad).
You're still reading it at every power_on/off, which I generally
believe is superflouous.. Unless the hardware has some unusual
properties, a *fuse* value does not change at runtime and doing it
once should be perfectly sufficient
That said, this is not a hill to die on..
Konrad
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding
2025-10-22 16:28 ` Krzysztof Kozlowski
@ 2025-11-06 14:50 ` Vikash Garodia
0 siblings, 0 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-11-06 14:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, Konrad Dybcio, Dikshita Agarwal,
Abhinav Kumar, Bryan O'Donoghue, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy
On 10/22/2025 9:58 PM, Krzysztof Kozlowski wrote:
> On 22/10/2025 17:36, Konrad Dybcio wrote:
>>>
>>> [ 1.361157] pc : qcom_smmu_write_s2cr+0x64/0xa4
>>> [ 1.361165] lr : arm_smmu_write_s2cr+0x2c/0xbc
>>> [ 1.361168] sp : ffff80008005b8f0
>>> [ 1.361169] x29: ffff80008005b8f0 x28: 0000000000000000 x27: ffffc7f252f45320
>>> ....
>>> [ 1.361195] x2 : ffff800081200c48 x1 : 0000000000000048 x0 : ffff800081200000
>>> [ 1.361198] Call trace:
>>> [ 1.361199] qcom_smmu_write_s2cr+0x64/0xa4 (P)
>>> [ 1.361203] arm_smmu_master_install_s2crs+0x7c/0xac
>>> [ 1.361207] arm_smmu_attach_dev+0xb0/0x1d4
>>>
>>> Could you please suggest on listing the iommu items ? I did not find the
>>> relevant references in other bindings where flexible iommus is being listed.
>>
>> Krzysztof would probably like to see what I believe someone else somewhere
>> sometime suggested in the iommus discussions (sorry it's not possible to
>> keep track of it all), where the DT can list every possible required iommu
>> sid, but the driver ensures only the ones that are necessary are utilized.
>>
>> This will require big changes to the iommu framework though, I'm afraid
>>
>>>> I already asked this.
>>>>
>>>>> +
>>>>> + memory-region:
>>>>> + minItems: 1
>>>>> + maxItems: 2
>>>>
>>>> Same comment. I already asked this about iommus.
>>>
>>> Same here, there aren't any bindings which lists for flexible memory-region.
>>> Please suggest if there are any such references.
>>
>> Similarly, we can define the additional memory region that's necessary
>> for $reasons and leave it unused in the driver (actually I don't know
>> why there may be two, but let's assume it's a QTEE/noQTEE detail), because
>> for the hw to operate, it must be set up by some entity in the system
>> either way (i.e. the memory is reserved even if it's not done by Linux)
>
>
> Another point is pretty obvious: if one claims that
> iommus/memory-regions list is flexible - some elements are optional -
> then clearly there is a distinction which elements are mandatory and
> which are optional. So there is difference between elements of the
> array. If there is a difference, they all must be explicitly listed,
> like every other list (clocks, resets etc) property. Writing bindings
> doc also defines this rule.
>
I would like to describe the video bindings covering all the interfaces,
including the secure stream ids. For this to do, i would have to wait
for [1] to conclude. Will put up a new revision on this series, to
exclude the binding patch and the one which enables kaanapali. That way
we can have the driver prepared for vpu4, while kaanapali binding and
patch to enable it in driver can be raised separately later once [1] is
concluded.
[1]
https://lore.kernel.org/all/cover.1762235099.git.charan.kalla@oss.qualcomm.com/
Regards,
Vikash
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform
2025-10-22 6:07 ` Vikash Garodia
@ 2025-11-10 7:45 ` Vikash Garodia
0 siblings, 0 replies; 32+ messages in thread
From: Vikash Garodia @ 2025-11-10 7:45 UTC (permalink / raw)
To: Nicolas Dufresne, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Dmitry Baryshkov, Konrad Dybcio
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel,
Vishnu Reddy, Bryan O'Donoghue
On 10/22/2025 11:37 AM, Vikash Garodia wrote:
> Hello Nicolas,
>
> On 10/17/2025 8:06 PM, Nicolas Dufresne wrote:
>> Hi Vikash,
>>
>> Le vendredi 17 octobre 2025 à 19:46 +0530, Vikash Garodia a
>>> [ 350.438406] qcom-iris 2000000.video-codec: invalid plane
>>> [ 350.447079] qcom-iris 2000000.video-codec: invalid plane
>>> [ 350.458821] qcom-iris 2000000.video-codec: invalid plane
>>> [ 350.465860] qcom-iris 2000000.video-codec: invalid plane
>>
>> Just a highlight, the driver should only print stuff on default log level if
>> something is malfunctioning. uAPI miss-use should only be trace on loglevel
>> manually enabled by the developers. Mind fixing this up while at it ? Hopefully
>> this will be obvious to you next time you encounter it.
>
> Agree, this specific log should not be part of default execution and more so
> when this is not malfunctioning. I would remove this log as i see it can be dropped.
This would be addressed with
https://lore.kernel.org/linux-media/20251110072429.1474615-1-busanna.reddy@oss.qualcomm.com/
Regards,
Vikash
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2025-11-10 7:45 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-17 14:16 [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 1/8] media: dt-bindings: qcom-kaanapali-iris: Add kaanapali video codec binding Vikash Garodia
2025-10-18 15:58 ` Krzysztof Kozlowski
2025-10-21 18:55 ` Vikash Garodia
2025-10-21 19:15 ` Krzysztof Kozlowski
2025-10-21 21:07 ` Vikash Garodia
2025-10-22 6:04 ` Krzysztof Kozlowski
2025-10-22 9:37 ` Dmitry Baryshkov
2025-10-22 14:51 ` Bryan O'Donoghue
2025-10-22 15:36 ` Konrad Dybcio
2025-10-22 16:28 ` Krzysztof Kozlowski
2025-11-06 14:50 ` Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 2/8] media: iris: Add support for multiple clock sources Vikash Garodia
2025-10-21 23:06 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 3/8] media: iris: Add support for multiple TZ content protection(CP) configs Vikash Garodia
2025-10-21 23:35 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 4/8] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
2025-10-21 23:25 ` Bryan O'Donoghue
2025-10-22 5:44 ` Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 5/8] media: iris: Move vpu register defines to common header file Vikash Garodia
2025-10-21 23:27 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 6/8] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
2025-10-21 23:29 ` Bryan O'Donoghue
2025-10-17 14:16 ` [PATCH v2 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
2025-10-17 14:16 ` [PATCH v2 8/8] media: iris: Add platform data for kaanapali Vikash Garodia
2025-10-21 23:39 ` Bryan O'Donoghue
2025-10-22 5:46 ` Vikash Garodia
2025-10-22 15:20 ` Bryan O'Donoghue
2025-10-17 14:36 ` [PATCH v2 0/8] media: iris: add support for video codecs on Qcom kaanapali platform Nicolas Dufresne
2025-10-22 6:07 ` Vikash Garodia
2025-11-10 7:45 ` Vikash Garodia
2025-10-22 17:26 ` Konrad Dybcio
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).