[PATCH v2] arm64: dts: rockchip: add USB 2.0 and 3.0 support on Ficus board

[PATCH v2] arm64: dts: rockchip: add USB 2.0 and 3.0 support on Ficus board

[Ezequiel Garcia]

From: Enric Balletbo i Serra <enric.balletbo@collabora.com>

The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and
another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB
controllers to enable theses devices.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
---
Changes from v1:
 * Provide voltage for vcc5v0_host and vcc3v3_pcie regulators
 * Provide vin_supply for vcc5v0_host.

 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 0d14183dd4a9..6295483b701f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -58,9 +58,24 @@
 		pinctrl-0 = <&pcie_drv>;
 		regulator-boot-on;
 		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
 		vin-supply = <&vcc3v3_sys>;
 	};
 
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc5v0_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
 	vdd_log: vdd-log {
 		compatible = "pwm-regulator";
 		pwms = <&pwm2 0 25000 0>;
@@ -454,6 +469,13 @@
 				<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 	};
+
+	usb2 {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins =
+				<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm2 {
@@ -487,6 +509,40 @@
 	status = "okay";
 };
 
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy1_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_xfer &uart0_cts>;
@@ -497,6 +553,40 @@
 	status = "okay";
 };
 
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
 &vopb {
 	status = "okay";
 };
-- 
2.18.0

Re: [PATCH v2] arm64: dts: rockchip: add USB 2.0 and 3.0 support on Ficus board

[Heiko Stuebner]

Hi Enric, Ezequiel,

Am Samstag, 14. Juli 2018, 19:09:22 CEST schrieb Ezequiel Garcia:
> From: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> 
> The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and
> another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB
> controllers to enable theses devices.
> 
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> Signed-off-by: Ezequiel Garcia <ezequiel-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> Changes from v1:
>  * Provide voltage for vcc5v0_host and vcc3v3_pcie regulators
>  * Provide vin_supply for vcc5v0_host.
> 
>  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> index 0d14183dd4a9..6295483b701f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> @@ -58,9 +58,24 @@
>  		pinctrl-0 = <&pcie_drv>;
>  		regulator-boot-on;
>  		regulator-name = "vcc3v3_pcie";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
>  		vin-supply = <&vcc3v3_sys>;
>  	};

I've split this out into a separate patch, as it isn't part of what
the commit message describes and thus should be separate
and applied both resulting patches for 4.19.

And also cleaned up a vendor-property that shouldn't be
part of mainline.


Heiko

Re: [PATCH v2] arm64: dts: rockchip: add USB 2.0 and 3.0 support on Ficus board

[Ezequiel Garcia]

On Mon, 2018-07-16 at 19:02 +0200, Heiko Stuebner wrote:
> Hi Enric, Ezequiel,
> 
> Am Samstag, 14. Juli 2018, 19:09:22 CEST schrieb Ezequiel Garcia:
> > From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> > 
> > The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and
> > another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB
> > controllers to enable theses devices.
> > 
> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> > Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
> > ---
> > Changes from v1:
> >  * Provide voltage for vcc5v0_host and vcc3v3_pcie regulators
> >  * Provide vin_supply for vcc5v0_host.
> > 
> >  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 90 +++++++++++++++++++
> >  1 file changed, 90 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > index 0d14183dd4a9..6295483b701f 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > @@ -58,9 +58,24 @@
> >  		pinctrl-0 = <&pcie_drv>;
> >  		regulator-boot-on;
> >  		regulator-name = "vcc3v3_pcie";
> > +		regulator-min-microvolt = <3300000>;
> > +		regulator-max-microvolt = <3300000>;
> >  		vin-supply = <&vcc3v3_sys>;
> >  	};
> 
> I've split this out into a separate patch, as it isn't part of what
> the commit message describes and thus should be separate
> and applied both resulting patches for 4.19.
> 
> And also cleaned up a vendor-property that shouldn't be
> part of mainline.
> 

Thanks a lot!