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[83.9.3.135]) by smtp.gmail.com with ESMTPSA id m11-20020ac24acb000000b004e95a1aca1bsm1880605lfp.87.2023.04.03.11.52.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Apr 2023 11:52:19 -0700 (PDT) Message-ID: <2492cd8f-8edc-4335-3af0-770e581e6355@linaro.org> Date: Mon, 3 Apr 2023 20:52:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes Content-Language: en-US To: Dmitry Baryshkov , Konrad Dybcio , Luca Weiss , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> <20230315-topic-lagoon_gpu-v1-4-a74cbec4ecfc@linaro.org> <22cfb674-eb2b-ff77-da87-cf6b520e592d@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 3.04.2023 20:50, Dmitry Baryshkov wrote: > On 18/03/2023 15:45, Konrad Dybcio wrote: >> >> >> On 17.03.2023 09:56, Luca Weiss wrote: >>> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that >>>> the A619 needs to function properly. >>>> >>>> Co-developed-by: Luca Weiss >>>> Signed-off-by: Konrad Dybcio >>>> Signed-off-by: Konrad Dybcio >>>> --- >> [...] >> >>> What about adding interconnect already? I also have opp-peak-kBps >>> additions in the opp table for that. I'll attach the diff I have at the >>> end of the email. >> I believe the GMU takes care of it internally (or at least should) >> with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table() > > We should still declare the interconnects. If at some point we attempt to fill these tables in a proper way, the interconnects will be required to get addresses of the nodes. A619 has all the "proper" data filled in. This should arguably be switched to per-SoC and not per-GPU btw. The interconnect endpoints should be looked up through the cmd_db function like Bjorn did in the A690 patchset. Konrad > >> >> >> [...] >> >>>>   +        adreno_smmu: iommu@3d40000 { >>> >>> This and gmu should be above gpucc @3d90000? >> Absolutely. >> >> Konrad >>> >>>> +            compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; >>>> +            reg = <0 0x03d40000 0 0x10000>; >>>> +            #iommu-cells = <1>; >>>> +            #global-interrupts = <2>; >>>> +            interrupts = , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     , >>>> +                     ; >>>> + >>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>, >>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; >>>> +            clock-names = "ahb", >>>> +                      "bus", >>>> +                      "iface"; >>>> + >>>> +            power-domains = <&gpucc GPU_CX_GDSC>; >>>> +        }; >>>> + >>>> +        gmu: gmu@3d6a000 { >>>> +            compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; >>>> +            reg = <0 0x03d6a000 0 0x31000>, >>>> +                  <0 0x0b290000 0 0x10000>, >>>> +                  <0 0x0b490000 0 0x10000>; >>>> +            reg-names = "gmu", >>>> +                    "gmu_pdc", >>>> +                    "gmu_pdc_seq"; >>>> + >>>> +            interrupts = , >>>> +                     ; >>>> +            interrupt-names = "hfi", >>>> +                      "gmu"; >>>> + >>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>, >>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>, >>>> +                 <&gpucc GPU_CC_CXO_CLK>, >>>> +                 <&gcc GCC_DDRSS_GPU_AXI_CLK>, >>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; >>>> +            clock-names = "ahb", >>>> +                      "gmu", >>>> +                      "cxo", >>>> +                      "axi", >>>> +                      "memnoc"; >>>> + >>>> +            power-domains = <&gpucc GPU_CX_GDSC>, >>>> +                    <&gpucc GPU_GX_GDSC>; >>>> +            power-domain-names = "cx", >>>> +                         "gx"; >>>> + >>>> +            iommus = <&adreno_smmu 5>; >>>> + >>>> +            operating-points-v2 = <&gmu_opp_table>; >>>> + >>>> +            status = "disabled"; >>>> + >>>> +            gmu_opp_table: opp-table { >>>> +                compatible = "operating-points-v2"; >>>> + >>>> +                opp-200000000 { >>>> +                    opp-hz = /bits/ 64 <200000000>; >>>> +                    opp-level = ; >>>> +                }; >>>> +            }; >>>> +        }; >>>> + >>>>           mpss: remoteproc@4080000 { >>>>               compatible = "qcom,sm6350-mpss-pas"; >>>>               reg = <0x0 0x04080000 0x0 0x4040>; >>>> >>>> --  >>>> 2.39.2 >>> >>> Here's the diff I have for interconnect on top of this: >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> index 4954cbc2c0fc..51c5ac679a32 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 { >>>               iommus = <&adreno_smmu 0>; >>>               operating-points-v2 = <&gpu_opp_table>; >>>               qcom,gmu = <&gmu>; >>> +            interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>; >>> +            interconnect-names = "gfx-mem"; >>>               nvmem-cells = <&gpu_speed_bin>; >>>               nvmem-cell-names = "speed_bin"; >>>   @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table { >>>                   opp-850000000 { >>>                       opp-hz = /bits/ 64 <850000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <8371200>; >>>                       opp-supported-hw = <0x02>; >>>                   }; >>>                     opp-800000000 { >>>                       opp-hz = /bits/ 64 <800000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <8371200>; >>>                       opp-supported-hw = <0x04>; >>>                   }; >>>                     opp-650000000 { >>>                       opp-hz = /bits/ 64 <650000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <6220000>; >>>                       opp-supported-hw = <0x08>; >>>                   }; >>>                     opp-565000000 { >>>                       opp-hz = /bits/ 64 <565000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <5412000>; >>>                       opp-supported-hw = <0x10>; >>>                   }; >>>                     opp-430000000 { >>>                       opp-hz = /bits/ 64 <430000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <4068000>; >>>                       opp-supported-hw = <0xff>; >>>                   }; >>>                     opp-355000000 { >>>                       opp-hz = /bits/ 64 <355000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <3072000>; >>>                       opp-supported-hw = <0xff>; >>>                   }; >>>                     opp-253000000 { >>>                       opp-hz = /bits/ 64 <253000000>; >>>                       opp-level = ; >>> +                    opp-peak-kBps = <2188000>; >>>                       opp-supported-hw = <0xff>; >>>                   }; >>>               }; >>> >