[PATCH 0/5] SM6350 GPU

[PATCH 0/5] SM6350 GPU

[Konrad Dybcio]

Add all the required nodes for SM6350's A619 and fix up its GPUCC
bindings.

This has been ready for like 1.5y now, time to finally merge it as
the display part will take some more time (due to the HW catalog rework).

Depends on (bindings, admittedly I could have organized it better):
https://lore.kernel.org/linux-arm-msm/20230314-topic-nvmem_compats-v1-0-508100c17603@linaro.org/#t

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (5):
      dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names
      arm64: dts: qcom: sm6350: Add GPUCC node
      arm64: dts: qcom: sm6350: Add QFPROM node
      arm64: dts: qcom: sm6350: Add GPU nodes
      arm64: dts: qcom: sm6350: Fix ZAP region

 .../devicetree/bindings/clock/qcom,gpucc.yaml      |  29 +++-
 arch/arm64/boot/dts/qcom/sm6350.dtsi               | 177 ++++++++++++++++++++-
 2 files changed, 197 insertions(+), 9 deletions(-)
---
base-commit: 225b6b81afe63b3850b7cee0a3590f51144f2a75
change-id: 20230315-topic-lagoon_gpu-8c2abccbc6eb

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names

[Konrad Dybcio]

SM6350 GPUCC uses the same clock names as the rest of the gang, except
without a _src suffix. Account for that.

Fixes: 7b91b9d8cc6c ("dt-bindings: clock: add SM6350 QCOM Graphics clock bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../devicetree/bindings/clock/qcom,gpucc.yaml      | 29 +++++++++++++++++++---
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index db53eb288995..d209060a619d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -43,10 +43,8 @@ properties:
       - description: GPLL0 div branch source
 
   clock-names:
-    items:
-      - const: bi_tcxo
-      - const: gcc_gpu_gpll0_clk_src
-      - const: gcc_gpu_gpll0_div_clk_src
+    minItems: 3
+    maxItems: 3
 
   '#clock-cells':
     const: 1
@@ -71,6 +69,29 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          items:
+            - const: qcom,sm6350-gpucc
+
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: bi_tcxo
+            - const: gcc_gpu_gpll0_clk
+            - const: gcc_gpu_gpll0_div_clk
+
+    else:
+      properties:
+        clock-names:
+          items:
+            - const: bi_tcxo
+            - const: gcc_gpu_gpll0_clk_src
+            - const: gcc_gpu_gpll0_div_clk_src
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-sdm845.h>

-- 
2.39.2

Re: [PATCH 1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names

[Krzysztof Kozlowski]

On 16/03/2023 12:16, Konrad Dybcio wrote:
> SM6350 GPUCC uses the same clock names as the rest of the gang, except
> without a _src suffix. Account for that.

Why not fixing the names instead (to use the same)? If the clocks are
the same, why using different names for the inputs? To remind - these
are not names of clocks in GCC, but names of clock inputs to the device.

> 
> Fixes: 7b91b9d8cc6c ("dt-bindings: clock: add SM6350 QCOM Graphics clock bindings")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../devicetree/bindings/clock/qcom,gpucc.yaml      | 29 +++++++++++++++++++---
>  1 file changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> index db53eb288995..d209060a619d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> @@ -43,10 +43,8 @@ properties:
>        - description: GPLL0 div branch source
>  
>    clock-names:
> -    items:
> -      - const: bi_tcxo
> -      - const: gcc_gpu_gpll0_clk_src
> -      - const: gcc_gpu_gpll0_div_clk_src
> +    minItems: 3

Drop minItems, not needed as it is implied by maxItems.

> +    maxItems: 3
>  
>    '#clock-cells':
>      const: 1
> @@ -71,6 +69,29 @@ required:
>  
>  additionalProperties: false
>
> 

Best regards,
Krzysztof

Re: [PATCH 1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names

[Konrad Dybcio]

On 17.03.2023 09:37, Krzysztof Kozlowski wrote:
> On 16/03/2023 12:16, Konrad Dybcio wrote:
>> SM6350 GPUCC uses the same clock names as the rest of the gang, except
>> without a _src suffix. Account for that.
> 
> Why not fixing the names instead (to use the same)? If the clocks are
> the same, why using different names for the inputs? To remind - these
> are not names of clocks in GCC, but names of clock inputs to the device.
Considering SM6350 is the only used of SM6350_GPUCC and it's not yet
in next and I don't think any other project using devicetree has
Adreno up on any platform, let alone this one, I suppose the ABI could
be broken and the driver could be made to expect the more common set
of names? Or I could transition it to index-based lookup?

Konrad
> 
>>
>> Fixes: 7b91b9d8cc6c ("dt-bindings: clock: add SM6350 QCOM Graphics clock bindings")
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>  .../devicetree/bindings/clock/qcom,gpucc.yaml      | 29 +++++++++++++++++++---
>>  1 file changed, 25 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>> index db53eb288995..d209060a619d 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>> @@ -43,10 +43,8 @@ properties:
>>        - description: GPLL0 div branch source
>>  
>>    clock-names:
>> -    items:
>> -      - const: bi_tcxo
>> -      - const: gcc_gpu_gpll0_clk_src
>> -      - const: gcc_gpu_gpll0_div_clk_src
>> +    minItems: 3
> 
> Drop minItems, not needed as it is implied by maxItems.
> 
>> +    maxItems: 3
>>  
>>    '#clock-cells':
>>      const: 1
>> @@ -71,6 +69,29 @@ required:
>>  
>>  additionalProperties: false
>>
>>
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names

[Konrad Dybcio]

On 17.03.2023 13:11, Konrad Dybcio wrote:
> 
> 
> On 17.03.2023 09:37, Krzysztof Kozlowski wrote:
>> On 16/03/2023 12:16, Konrad Dybcio wrote:
>>> SM6350 GPUCC uses the same clock names as the rest of the gang, except
>>> without a _src suffix. Account for that.
>>
>> Why not fixing the names instead (to use the same)? If the clocks are
>> the same, why using different names for the inputs? To remind - these
>> are not names of clocks in GCC, but names of clock inputs to the device.
> Considering SM6350 is the only used of SM6350_GPUCC and it's not yet
> in next and I don't think any other project using devicetree has
> Adreno up on any platform, let alone this one, I suppose the ABI could
> be broken and the driver could be made to expect the more common set
> of names? Or I could transition it to index-based lookup?
Comments, please?

Konrad
> 
> Konrad
>>
>>>
>>> Fixes: 7b91b9d8cc6c ("dt-bindings: clock: add SM6350 QCOM Graphics clock bindings")
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>>  .../devicetree/bindings/clock/qcom,gpucc.yaml      | 29 +++++++++++++++++++---
>>>  1 file changed, 25 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>>> index db53eb288995..d209060a619d 100644
>>> --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>>> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>>> @@ -43,10 +43,8 @@ properties:
>>>        - description: GPLL0 div branch source
>>>  
>>>    clock-names:
>>> -    items:
>>> -      - const: bi_tcxo
>>> -      - const: gcc_gpu_gpll0_clk_src
>>> -      - const: gcc_gpu_gpll0_div_clk_src
>>> +    minItems: 3
>>
>> Drop minItems, not needed as it is implied by maxItems.
>>
>>> +    maxItems: 3
>>>  
>>>    '#clock-cells':
>>>      const: 1
>>> @@ -71,6 +69,29 @@ required:
>>>  
>>>  additionalProperties: false
>>>
>>>
>>
>> Best regards,
>> Krzysztof
>>

[PATCH 2/5] arm64: dts: qcom: sm6350: Add GPUCC node

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@somainline.org>

Add and configure a node for the GPU clock controller.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c46bb6dab6a1..523c7edfa4b3 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -1125,6 +1126,20 @@ compute-cb@5 {
 			};
 		};
 
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,sm6350-gpucc";
+			reg = <0 0x03d90000 0 0x9000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk",
+				      "gcc_gpu_gpll0_div_clk";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm6350-mpss-pas";
 			reg = <0x0 0x04080000 0x0 0x4040>;

-- 
2.39.2

Re: [PATCH 2/5] arm64: dts: qcom: sm6350: Add GPUCC node

[Luca Weiss]

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add and configure a node for the GPU clock controller.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index c46bb6dab6a1..523c7edfa4b3 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -5,6 +5,7 @@
>   */
>  
>  #include <dt-bindings/clock/qcom,gcc-sm6350.h>
> +#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sm6350-camcc.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
> @@ -1125,6 +1126,20 @@ compute-cb@5 {
>  			};
>  		};
>  
> +		gpucc: clock-controller@3d90000 {
> +			compatible = "qcom,sm6350-gpucc";
> +			reg = <0 0x03d90000 0 0x9000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_GPU_GPLL0_CLK>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
> +			clock-names = "bi_tcxo",
> +				      "gcc_gpu_gpll0_clk",
> +				      "gcc_gpu_gpll0_div_clk";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		mpss: remoteproc@4080000 {
>  			compatible = "qcom,sm6350-mpss-pas";
>  			reg = <0x0 0x04080000 0x0 0x4040>;
>
> -- 
> 2.39.2

[PATCH 3/5] arm64: dts: qcom: sm6350: Add QFPROM node

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@somainline.org>

Add a node for the QFPROM NVMEM hw and define the GPU fuse.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 523c7edfa4b3..60b68d305e53 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -637,6 +637,18 @@ ipcc: mailbox@408000 {
 			#mbox-cells = <2>;
 		};
 
+		qfprom: qfprom@784000 {
+			compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
+			reg = <0 0x00784000 0 0x3000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpu_speed_bin: gpu_speed_bin@2015 {
+				reg = <0x2015 0x1>;
+				bits = <0 8>;
+			};
+		};
+
 		rng: rng@793000 {
 			compatible = "qcom,prng-ee";
 			reg = <0 0x00793000 0 0x1000>;

-- 
2.39.2

Re: [PATCH 3/5] arm64: dts: qcom: sm6350: Add QFPROM node

[Luca Weiss]

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add a node for the QFPROM NVMEM hw and define the GPU fuse.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 523c7edfa4b3..60b68d305e53 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -637,6 +637,18 @@ ipcc: mailbox@408000 {
>  			#mbox-cells = <2>;
>  		};
>  
> +		qfprom: qfprom@784000 {
> +			compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
> +			reg = <0 0x00784000 0 0x3000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			gpu_speed_bin: gpu_speed_bin@2015 {

gpu-speed-bin@2015 ?

With that fixed:

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>

> +				reg = <0x2015 0x1>;
> +				bits = <0 8>;
> +			};
> +		};
> +
>  		rng: rng@793000 {
>  			compatible = "qcom,prng-ee";
>  			reg = <0 0x00793000 0 0x1000>;
>
> -- 
> 2.39.2

Re: [PATCH 3/5] arm64: dts: qcom: sm6350: Add QFPROM node

[Konrad Dybcio]

On 17.03.2023 09:50, Luca Weiss wrote:
> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>
>> Add a node for the QFPROM NVMEM hw and define the GPU fuse.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> index 523c7edfa4b3..60b68d305e53 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> @@ -637,6 +637,18 @@ ipcc: mailbox@408000 {
>>  			#mbox-cells = <2>;
>>  		};
>>  
>> +		qfprom: qfprom@784000 {
>> +			compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
>> +			reg = <0 0x00784000 0 0x3000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			gpu_speed_bin: gpu_speed_bin@2015 {
> 
> gpu-speed-bin@2015 ?
Ack
Konrad
> 
> With that fixed:
> 
> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
> 
>> +				reg = <0x2015 0x1>;
>> +				bits = <0 8>;
>> +			};
>> +		};
>> +
>>  		rng: rng@793000 {
>>  			compatible = "qcom,prng-ee";
>>  			reg = <0 0x00793000 0 0x1000>;
>>
>> -- 
>> 2.39.2
> 

[PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@somainline.org>

Add Adreno, GPU SMMU and GMU nodes to hook up everything that
the A619 needs to function properly.

Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 60b68d305e53..e967d06b0ad4 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1138,6 +1138,74 @@ compute-cb@5 {
 			};
 		};
 
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-619.0", "qcom,adreno";
+			reg = <0 0x03d00000 0 0x40000>,
+			      <0 0x03d9e000 0 0x1000>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem";
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+			operating-points-v2 = <&gpu_opp_table>;
+			qcom,gmu = <&gmu>;
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
+			status = "disabled";
+
+			zap-shader {
+				memory-region = <&pil_gpu_mem>;
+			};
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-850000000 {
+					opp-hz = /bits/ 64 <850000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-supported-hw = <0x02>;
+				};
+
+				opp-800000000 {
+					opp-hz = /bits/ 64 <800000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-supported-hw = <0x04>;
+				};
+
+				opp-650000000 {
+					opp-hz = /bits/ 64 <650000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-supported-hw = <0x08>;
+				};
+
+				opp-565000000 {
+					opp-hz = /bits/ 64 <565000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x10>;
+				};
+
+				opp-430000000 {
+					opp-hz = /bits/ 64 <430000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0xff>;
+				};
+
+				opp-355000000 {
+					opp-hz = /bits/ 64 <355000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0xff>;
+				};
+
+				opp-253000000 {
+					opp-hz = /bits/ 64 <253000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0xff>;
+				};
+			};
+		};
+
+
 		gpucc: clock-controller@3d90000 {
 			compatible = "qcom,sm6350-gpucc";
 			reg = <0 0x03d90000 0 0x9000>;
@@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3d40000 {
+			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0 0x03d40000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+			clock-names = "ahb",
+				      "bus",
+				      "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@3d6a000 {
+			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
+			reg = <0 0x03d6a000 0 0x31000>,
+			      <0 0x0b290000 0 0x10000>,
+			      <0 0x0b490000 0 0x10000>;
+			reg-names = "gmu",
+				    "gmu_pdc",
+				    "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi",
+					  "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "axi",
+				      "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			status = "disabled";
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm6350-mpss-pas";
 			reg = <0x0 0x04080000 0x0 0x4040>;

-- 
2.39.2

Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Luca Weiss]

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
> the A619 needs to function properly.
>
> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>

I believe my signoff is missing here since I'm Co-developed-by:

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>

> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 60b68d305e53..e967d06b0ad4 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1138,6 +1138,74 @@ compute-cb@5 {
>  			};
>  		};
>  
> +		gpu: gpu@3d00000 {
> +			compatible = "qcom,adreno-619.0", "qcom,adreno";
> +			reg = <0 0x03d00000 0 0x40000>,
> +			      <0 0x03d9e000 0 0x1000>;
> +			reg-names = "kgsl_3d0_reg_memory",
> +				    "cx_mem";
> +			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			iommus = <&adreno_smmu 0>;
> +			operating-points-v2 = <&gpu_opp_table>;
> +			qcom,gmu = <&gmu>;
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";
> +
> +			status = "disabled";
> +
> +			zap-shader {
> +				memory-region = <&pil_gpu_mem>;
> +			};
> +
> +			gpu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-850000000 {
> +					opp-hz = /bits/ 64 <850000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-supported-hw = <0x02>;
> +				};
> +
> +				opp-800000000 {
> +					opp-hz = /bits/ 64 <800000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-supported-hw = <0x04>;
> +				};
> +
> +				opp-650000000 {
> +					opp-hz = /bits/ 64 <650000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x08>;
> +				};
> +
> +				opp-565000000 {
> +					opp-hz = /bits/ 64 <565000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x10>;
> +				};
> +
> +				opp-430000000 {
> +					opp-hz = /bits/ 64 <430000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-355000000 {
> +					opp-hz = /bits/ 64 <355000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-253000000 {
> +					opp-hz = /bits/ 64 <253000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +			};
> +		};
> +
> +
>  		gpucc: clock-controller@3d90000 {
>  			compatible = "qcom,sm6350-gpucc";
>  			reg = <0 0x03d90000 0 0x9000>;
> @@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3d40000 {
> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +			reg = <0 0x03d40000 0 0x10000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <2>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "bus",
> +				      "iface";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>;
> +		};
> +
> +		gmu: gmu@3d6a000 {
> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
> +			reg = <0 0x03d6a000 0 0x31000>,
> +			      <0 0x0b290000 0 0x10000>,
> +			      <0 0x0b490000 0 0x10000>;
> +			reg-names = "gmu",
> +				    "gmu_pdc",
> +				    "gmu_pdc_seq";
> +
> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hfi",
> +					  "gmu";
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_CXO_CLK>,
> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "gmu",
> +				      "cxo",
> +				      "axi",
> +				      "memnoc";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>,
> +					<&gpucc GPU_GX_GDSC>;
> +			power-domain-names = "cx",
> +					     "gx";
> +
> +			iommus = <&adreno_smmu 5>;
> +
> +			operating-points-v2 = <&gmu_opp_table>;
> +
> +			status = "disabled";
> +
> +			gmu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-200000000 {
> +					opp-hz = /bits/ 64 <200000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
>  		mpss: remoteproc@4080000 {
>  			compatible = "qcom,sm6350-mpss-pas";
>  			reg = <0x0 0x04080000 0x0 0x4040>;
>
> -- 
> 2.39.2

Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Luca Weiss]

On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
> the A619 needs to function properly.
>
> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 60b68d305e53..e967d06b0ad4 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1138,6 +1138,74 @@ compute-cb@5 {
>  			};
>  		};
>  
> +		gpu: gpu@3d00000 {
> +			compatible = "qcom,adreno-619.0", "qcom,adreno";
> +			reg = <0 0x03d00000 0 0x40000>,
> +			      <0 0x03d9e000 0 0x1000>;
> +			reg-names = "kgsl_3d0_reg_memory",
> +				    "cx_mem";
> +			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			iommus = <&adreno_smmu 0>;
> +			operating-points-v2 = <&gpu_opp_table>;
> +			qcom,gmu = <&gmu>;
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";

What about adding interconnect already? I also have opp-peak-kBps
additions in the opp table for that. I'll attach the diff I have at the
end of the email.

> +
> +			status = "disabled";
> +
> +			zap-shader {
> +				memory-region = <&pil_gpu_mem>;
> +			};
> +
> +			gpu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-850000000 {
> +					opp-hz = /bits/ 64 <850000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-supported-hw = <0x02>;
> +				};
> +
> +				opp-800000000 {
> +					opp-hz = /bits/ 64 <800000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-supported-hw = <0x04>;
> +				};
> +
> +				opp-650000000 {
> +					opp-hz = /bits/ 64 <650000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x08>;
> +				};
> +
> +				opp-565000000 {
> +					opp-hz = /bits/ 64 <565000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x10>;
> +				};
> +
> +				opp-430000000 {
> +					opp-hz = /bits/ 64 <430000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-355000000 {
> +					opp-hz = /bits/ 64 <355000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +
> +				opp-253000000 {
> +					opp-hz = /bits/ 64 <253000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0xff>;
> +				};
> +			};
> +		};
> +
> +
>  		gpucc: clock-controller@3d90000 {
>  			compatible = "qcom,sm6350-gpucc";
>  			reg = <0 0x03d90000 0 0x9000>;
> @@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3d40000 {

This and gmu should be above gpucc @3d90000?

> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
> +			reg = <0 0x03d40000 0 0x10000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <2>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "bus",
> +				      "iface";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>;
> +		};
> +
> +		gmu: gmu@3d6a000 {
> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
> +			reg = <0 0x03d6a000 0 0x31000>,
> +			      <0 0x0b290000 0 0x10000>,
> +			      <0 0x0b490000 0 0x10000>;
> +			reg-names = "gmu",
> +				    "gmu_pdc",
> +				    "gmu_pdc_seq";
> +
> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hfi",
> +					  "gmu";
> +
> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_CXO_CLK>,
> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +			clock-names = "ahb",
> +				      "gmu",
> +				      "cxo",
> +				      "axi",
> +				      "memnoc";
> +
> +			power-domains = <&gpucc GPU_CX_GDSC>,
> +					<&gpucc GPU_GX_GDSC>;
> +			power-domain-names = "cx",
> +					     "gx";
> +
> +			iommus = <&adreno_smmu 5>;
> +
> +			operating-points-v2 = <&gmu_opp_table>;
> +
> +			status = "disabled";
> +
> +			gmu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-200000000 {
> +					opp-hz = /bits/ 64 <200000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
>  		mpss: remoteproc@4080000 {
>  			compatible = "qcom,sm6350-mpss-pas";
>  			reg = <0x0 0x04080000 0x0 0x4040>;
>
> -- 
> 2.39.2

Here's the diff I have for interconnect on top of this:

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 4954cbc2c0fc..51c5ac679a32 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
 			iommus = <&adreno_smmu 0>;
 			operating-points-v2 = <&gpu_opp_table>;
 			qcom,gmu = <&gmu>;
+			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
+			interconnect-names = "gfx-mem";
 			nvmem-cells = <&gpu_speed_bin>;
 			nvmem-cell-names = "speed_bin";
 
@@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
 				opp-850000000 {
 					opp-hz = /bits/ 64 <850000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <8371200>;
 					opp-supported-hw = <0x02>;
 				};
 
 				opp-800000000 {
 					opp-hz = /bits/ 64 <800000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <8371200>;
 					opp-supported-hw = <0x04>;
 				};
 
 				opp-650000000 {
 					opp-hz = /bits/ 64 <650000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <6220000>;
 					opp-supported-hw = <0x08>;
 				};
 
 				opp-565000000 {
 					opp-hz = /bits/ 64 <565000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <5412000>;
 					opp-supported-hw = <0x10>;
 				};
 
 				opp-430000000 {
 					opp-hz = /bits/ 64 <430000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <4068000>;
 					opp-supported-hw = <0xff>;
 				};
 
 				opp-355000000 {
 					opp-hz = /bits/ 64 <355000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <3072000>;
 					opp-supported-hw = <0xff>;
 				};
 
 				opp-253000000 {
 					opp-hz = /bits/ 64 <253000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <2188000>;
 					opp-supported-hw = <0xff>;
 				};
 			};

Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Konrad Dybcio]

On 17.03.2023 09:56, Luca Weiss wrote:
> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>
>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>> the A619 needs to function properly.
>>
>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]

> What about adding interconnect already? I also have opp-peak-kBps
> additions in the opp table for that. I'll attach the diff I have at the
> end of the email.
I believe the GMU takes care of it internally (or at least should)
with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()


[...]

>>  
>> +		adreno_smmu: iommu@3d40000 {
> 
> This and gmu should be above gpucc @3d90000?
Absolutely.

Konrad
> 
>> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>> +			reg = <0 0x03d40000 0 0x10000>;
>> +			#iommu-cells = <1>;
>> +			#global-interrupts = <2>;
>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "bus",
>> +				      "iface";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>;
>> +		};
>> +
>> +		gmu: gmu@3d6a000 {
>> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>> +			reg = <0 0x03d6a000 0 0x31000>,
>> +			      <0 0x0b290000 0 0x10000>,
>> +			      <0 0x0b490000 0 0x10000>;
>> +			reg-names = "gmu",
>> +				    "gmu_pdc",
>> +				    "gmu_pdc_seq";
>> +
>> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hfi",
>> +					  "gmu";
>> +
>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>> +				 <&gpucc GPU_CC_CXO_CLK>,
>> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>> +			clock-names = "ahb",
>> +				      "gmu",
>> +				      "cxo",
>> +				      "axi",
>> +				      "memnoc";
>> +
>> +			power-domains = <&gpucc GPU_CX_GDSC>,
>> +					<&gpucc GPU_GX_GDSC>;
>> +			power-domain-names = "cx",
>> +					     "gx";
>> +
>> +			iommus = <&adreno_smmu 5>;
>> +
>> +			operating-points-v2 = <&gmu_opp_table>;
>> +
>> +			status = "disabled";
>> +
>> +			gmu_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-200000000 {
>> +					opp-hz = /bits/ 64 <200000000>;
>> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> +				};
>> +			};
>> +		};
>> +
>>  		mpss: remoteproc@4080000 {
>>  			compatible = "qcom,sm6350-mpss-pas";
>>  			reg = <0x0 0x04080000 0x0 0x4040>;
>>
>> -- 
>> 2.39.2
> 
> Here's the diff I have for interconnect on top of this:
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 4954cbc2c0fc..51c5ac679a32 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>  			iommus = <&adreno_smmu 0>;
>  			operating-points-v2 = <&gpu_opp_table>;
>  			qcom,gmu = <&gmu>;
> +			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
> +			interconnect-names = "gfx-mem";
>  			nvmem-cells = <&gpu_speed_bin>;
>  			nvmem-cell-names = "speed_bin";
>  
> @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>  				opp-850000000 {
>  					opp-hz = /bits/ 64 <850000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x02>;
>  				};
>  
>  				opp-800000000 {
>  					opp-hz = /bits/ 64 <800000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +					opp-peak-kBps = <8371200>;
>  					opp-supported-hw = <0x04>;
>  				};
>  
>  				opp-650000000 {
>  					opp-hz = /bits/ 64 <650000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-peak-kBps = <6220000>;
>  					opp-supported-hw = <0x08>;
>  				};
>  
>  				opp-565000000 {
>  					opp-hz = /bits/ 64 <565000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-peak-kBps = <5412000>;
>  					opp-supported-hw = <0x10>;
>  				};
>  
>  				opp-430000000 {
>  					opp-hz = /bits/ 64 <430000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-peak-kBps = <4068000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-355000000 {
>  					opp-hz = /bits/ 64 <355000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-peak-kBps = <3072000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  
>  				opp-253000000 {
>  					opp-hz = /bits/ 64 <253000000>;
>  					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-peak-kBps = <2188000>;
>  					opp-supported-hw = <0xff>;
>  				};
>  			};
> 

Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Dmitry Baryshkov]

On 18/03/2023 15:45, Konrad Dybcio wrote:
> 
> 
> On 17.03.2023 09:56, Luca Weiss wrote:
>> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>
>>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>>> the A619 needs to function properly.
>>>
>>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
> [...]
> 
>> What about adding interconnect already? I also have opp-peak-kBps
>> additions in the opp table for that. I'll attach the diff I have at the
>> end of the email.
> I believe the GMU takes care of it internally (or at least should)
> with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()

We should still declare the interconnects. If at some point we attempt 
to fill these tables in a proper way, the interconnects will be required 
to get addresses of the nodes.

> 
> 
> [...]
> 
>>>   
>>> +		adreno_smmu: iommu@3d40000 {
>>
>> This and gmu should be above gpucc @3d90000?
> Absolutely.
> 
> Konrad
>>
>>> +			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>>> +			reg = <0 0x03d40000 0 0x10000>;
>>> +			#iommu-cells = <1>;
>>> +			#global-interrupts = <2>;
>>> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>>> +			clock-names = "ahb",
>>> +				      "bus",
>>> +				      "iface";
>>> +
>>> +			power-domains = <&gpucc GPU_CX_GDSC>;
>>> +		};
>>> +
>>> +		gmu: gmu@3d6a000 {
>>> +			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>>> +			reg = <0 0x03d6a000 0 0x31000>,
>>> +			      <0 0x0b290000 0 0x10000>,
>>> +			      <0 0x0b490000 0 0x10000>;
>>> +			reg-names = "gmu",
>>> +				    "gmu_pdc",
>>> +				    "gmu_pdc_seq";
>>> +
>>> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>> +			interrupt-names = "hfi",
>>> +					  "gmu";
>>> +
>>> +			clocks = <&gpucc GPU_CC_AHB_CLK>,
>>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>>> +				 <&gpucc GPU_CC_CXO_CLK>,
>>> +				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>> +				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>>> +			clock-names = "ahb",
>>> +				      "gmu",
>>> +				      "cxo",
>>> +				      "axi",
>>> +				      "memnoc";
>>> +
>>> +			power-domains = <&gpucc GPU_CX_GDSC>,
>>> +					<&gpucc GPU_GX_GDSC>;
>>> +			power-domain-names = "cx",
>>> +					     "gx";
>>> +
>>> +			iommus = <&adreno_smmu 5>;
>>> +
>>> +			operating-points-v2 = <&gmu_opp_table>;
>>> +
>>> +			status = "disabled";
>>> +
>>> +			gmu_opp_table: opp-table {
>>> +				compatible = "operating-points-v2";
>>> +
>>> +				opp-200000000 {
>>> +					opp-hz = /bits/ 64 <200000000>;
>>> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>>   		mpss: remoteproc@4080000 {
>>>   			compatible = "qcom,sm6350-mpss-pas";
>>>   			reg = <0x0 0x04080000 0x0 0x4040>;
>>>
>>> -- 
>>> 2.39.2
>>
>> Here's the diff I have for interconnect on top of this:
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> index 4954cbc2c0fc..51c5ac679a32 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>>   			iommus = <&adreno_smmu 0>;
>>   			operating-points-v2 = <&gpu_opp_table>;
>>   			qcom,gmu = <&gmu>;
>> +			interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
>> +			interconnect-names = "gfx-mem";
>>   			nvmem-cells = <&gpu_speed_bin>;
>>   			nvmem-cell-names = "speed_bin";
>>   
>> @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>>   				opp-850000000 {
>>   					opp-hz = /bits/ 64 <850000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>> +					opp-peak-kBps = <8371200>;
>>   					opp-supported-hw = <0x02>;
>>   				};
>>   
>>   				opp-800000000 {
>>   					opp-hz = /bits/ 64 <800000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>> +					opp-peak-kBps = <8371200>;
>>   					opp-supported-hw = <0x04>;
>>   				};
>>   
>>   				opp-650000000 {
>>   					opp-hz = /bits/ 64 <650000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> +					opp-peak-kBps = <6220000>;
>>   					opp-supported-hw = <0x08>;
>>   				};
>>   
>>   				opp-565000000 {
>>   					opp-hz = /bits/ 64 <565000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +					opp-peak-kBps = <5412000>;
>>   					opp-supported-hw = <0x10>;
>>   				};
>>   
>>   				opp-430000000 {
>>   					opp-hz = /bits/ 64 <430000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> +					opp-peak-kBps = <4068000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   
>>   				opp-355000000 {
>>   					opp-hz = /bits/ 64 <355000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> +					opp-peak-kBps = <3072000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   
>>   				opp-253000000 {
>>   					opp-hz = /bits/ 64 <253000000>;
>>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +					opp-peak-kBps = <2188000>;
>>   					opp-supported-hw = <0xff>;
>>   				};
>>   			};
>>

-- 
With best wishes
Dmitry

Re: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes

[Konrad Dybcio]

On 3.04.2023 20:50, Dmitry Baryshkov wrote:
> On 18/03/2023 15:45, Konrad Dybcio wrote:
>>
>>
>> On 17.03.2023 09:56, Luca Weiss wrote:
>>> On Thu Mar 16, 2023 at 12:16 PM CET, Konrad Dybcio wrote:
>>>> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>>
>>>> Add Adreno, GPU SMMU and GMU nodes to hook up everything that
>>>> the A619 needs to function properly.
>>>>
>>>> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>> [...]
>>
>>> What about adding interconnect already? I also have opp-peak-kBps
>>> additions in the opp table for that. I'll attach the diff I have at the
>>> end of the email.
>> I believe the GMU takes care of it internally (or at least should)
>> with the bandwidth tables we send in a6xx_hfi.c : a6xx_hfi_send_bw_table()
> 
> We should still declare the interconnects. If at some point we attempt to fill these tables in a proper way, the interconnects will be required to get addresses of the nodes.
A619 has all the "proper" data filled in. This should arguably
be switched to per-SoC and not per-GPU btw.

The interconnect endpoints should be looked up through the cmd_db
function like Bjorn did in the A690 patchset.

Konrad
> 
>>
>>
>> [...]
>>
>>>>   +        adreno_smmu: iommu@3d40000 {
>>>
>>> This and gmu should be above gpucc @3d90000?
>> Absolutely.
>>
>> Konrad
>>>
>>>> +            compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
>>>> +            reg = <0 0x03d40000 0 0x10000>;
>>>> +            #iommu-cells = <1>;
>>>> +            #global-interrupts = <2>;
>>>> +            interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>>>> +
>>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>,
>>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
>>>> +            clock-names = "ahb",
>>>> +                      "bus",
>>>> +                      "iface";
>>>> +
>>>> +            power-domains = <&gpucc GPU_CX_GDSC>;
>>>> +        };
>>>> +
>>>> +        gmu: gmu@3d6a000 {
>>>> +            compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
>>>> +            reg = <0 0x03d6a000 0 0x31000>,
>>>> +                  <0 0x0b290000 0 0x10000>,
>>>> +                  <0 0x0b490000 0 0x10000>;
>>>> +            reg-names = "gmu",
>>>> +                    "gmu_pdc",
>>>> +                    "gmu_pdc_seq";
>>>> +
>>>> +            interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>>>> +            interrupt-names = "hfi",
>>>> +                      "gmu";
>>>> +
>>>> +            clocks = <&gpucc GPU_CC_AHB_CLK>,
>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>> +                 <&gpucc GPU_CC_CXO_CLK>,
>>>> +                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>>>> +                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
>>>> +            clock-names = "ahb",
>>>> +                      "gmu",
>>>> +                      "cxo",
>>>> +                      "axi",
>>>> +                      "memnoc";
>>>> +
>>>> +            power-domains = <&gpucc GPU_CX_GDSC>,
>>>> +                    <&gpucc GPU_GX_GDSC>;
>>>> +            power-domain-names = "cx",
>>>> +                         "gx";
>>>> +
>>>> +            iommus = <&adreno_smmu 5>;
>>>> +
>>>> +            operating-points-v2 = <&gmu_opp_table>;
>>>> +
>>>> +            status = "disabled";
>>>> +
>>>> +            gmu_opp_table: opp-table {
>>>> +                compatible = "operating-points-v2";
>>>> +
>>>> +                opp-200000000 {
>>>> +                    opp-hz = /bits/ 64 <200000000>;
>>>> +                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>>>> +                };
>>>> +            };
>>>> +        };
>>>> +
>>>>           mpss: remoteproc@4080000 {
>>>>               compatible = "qcom,sm6350-mpss-pas";
>>>>               reg = <0x0 0x04080000 0x0 0x4040>;
>>>>
>>>> -- 
>>>> 2.39.2
>>>
>>> Here's the diff I have for interconnect on top of this:
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> index 4954cbc2c0fc..51c5ac679a32 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
>>> @@ -1142,6 +1142,8 @@ gpu: gpu@3d00000 {
>>>               iommus = <&adreno_smmu 0>;
>>>               operating-points-v2 = <&gpu_opp_table>;
>>>               qcom,gmu = <&gmu>;
>>> +            interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &clk_virt SLAVE_EBI_CH0 0>;
>>> +            interconnect-names = "gfx-mem";
>>>               nvmem-cells = <&gpu_speed_bin>;
>>>               nvmem-cell-names = "speed_bin";
>>>   @@ -1157,42 +1159,49 @@ gpu_opp_table: opp-table {
>>>                   opp-850000000 {
>>>                       opp-hz = /bits/ 64 <850000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>>> +                    opp-peak-kBps = <8371200>;
>>>                       opp-supported-hw = <0x02>;
>>>                   };
>>>                     opp-800000000 {
>>>                       opp-hz = /bits/ 64 <800000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>>> +                    opp-peak-kBps = <8371200>;
>>>                       opp-supported-hw = <0x04>;
>>>                   };
>>>                     opp-650000000 {
>>>                       opp-hz = /bits/ 64 <650000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>>> +                    opp-peak-kBps = <6220000>;
>>>                       opp-supported-hw = <0x08>;
>>>                   };
>>>                     opp-565000000 {
>>>                       opp-hz = /bits/ 64 <565000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>>> +                    opp-peak-kBps = <5412000>;
>>>                       opp-supported-hw = <0x10>;
>>>                   };
>>>                     opp-430000000 {
>>>                       opp-hz = /bits/ 64 <430000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>> +                    opp-peak-kBps = <4068000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>                     opp-355000000 {
>>>                       opp-hz = /bits/ 64 <355000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>>> +                    opp-peak-kBps = <3072000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>                     opp-253000000 {
>>>                       opp-hz = /bits/ 64 <253000000>;
>>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>>> +                    opp-peak-kBps = <2188000>;
>>>                       opp-supported-hw = <0xff>;
>>>                   };
>>>               };
>>>
> 

[PATCH 5/5] arm64: dts: qcom: sm6350: Fix ZAP region

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@somainline.org>

The previous ZAP region definition was wrong. Fix it.
Note this is not a device-specific fixup, but a fixup to the generic
PIL load address.

Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index e967d06b0ad4..3fe4a5fa3021 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -466,11 +466,6 @@ pil_ipa_gsi_mem: memory@8b710000 {
 			no-map;
 		};
 
-		pil_gpu_mem: memory@8b715400 {
-			reg = <0 0x8b715400 0 0x2000>;
-			no-map;
-		};
-
 		pil_modem_mem: memory@8b800000 {
 			reg = <0 0x8b800000 0 0xf800000>;
 			no-map;
@@ -491,6 +486,11 @@ removed_region: memory@c0000000 {
 			no-map;
 		};
 
+		pil_gpu_mem: memory@f0d00000 {
+			reg = <0 0xf0d00000 0 0x1000>;
+			no-map;
+		};
+
 		debug_region: memory@ffb00000 {
 			reg = <0 0xffb00000 0 0xc0000>;
 			no-map;

-- 
2.39.2

Re: [PATCH 5/5] arm64: dts: qcom: sm6350: Fix ZAP region

[Luca Weiss]

On Thu Mar 16, 2023 at 12:17 PM CET, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@somainline.org>
>
> The previous ZAP region definition was wrong. Fix it.
> Note this is not a device-specific fixup, but a fixup to the generic
> PIL load address.
>
> Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index e967d06b0ad4..3fe4a5fa3021 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -466,11 +466,6 @@ pil_ipa_gsi_mem: memory@8b710000 {
>  			no-map;
>  		};
>  
> -		pil_gpu_mem: memory@8b715400 {
> -			reg = <0 0x8b715400 0 0x2000>;
> -			no-map;
> -		};
> -
>  		pil_modem_mem: memory@8b800000 {
>  			reg = <0 0x8b800000 0 0xf800000>;
>  			no-map;
> @@ -491,6 +486,11 @@ removed_region: memory@c0000000 {
>  			no-map;
>  		};
>  
> +		pil_gpu_mem: memory@f0d00000 {
> +			reg = <0 0xf0d00000 0 0x1000>;
> +			no-map;
> +		};
> +
>  		debug_region: memory@ffb00000 {
>  			reg = <0 0xffb00000 0 0xc0000>;
>  			no-map;
>
> -- 
> 2.39.2