From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
To: Borislav Petkov <bp@alien8.de>
Cc: dinguyen@kernel.org, matthew.gerlach@altera.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, tony.luck@intel.com,
linux-edac@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/6] EDAC/altera: Add IO96B ECC support for Agilex5 SoCFPGA
Date: Fri, 31 Oct 2025 19:52:41 +0800 [thread overview]
Message-ID: <24d2beec-129e-4545-b777-c1c717be956c@altera.com> (raw)
In-Reply-To: <20251030143051.GJaQN2m2fniYVRtBxn@fat_crate.local>
On 30/10/2025 10:30 pm, Borislav Petkov wrote:
> On Tue, Oct 28, 2025 at 05:22:30PM +0800,niravkumarlaxmidas.rabara@altera.com wrote:
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 39352b9b7a7e..33a9fccde2fe 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -410,6 +410,16 @@ config EDAC_ALTERA_SDRAM
>> preloader must initialize the SDRAM before loading
>> the kernel.
>>
>> +config EDAC_ALTERA_IO96B
>> + bool "Altera I096B ECC"
> Is this and the other new Kconfig symbols you're adding absolutely needed?
>
> IOW, why can't the driver simply load on that new hw without needing Kconfig
> symbols at all?
>
> What are they really saving?
>
> Thx.
>
> -- Regards/Gruss, Boris.
Hi Boris,
Thanks for your review.
Your point is absolutely valid — I was initially hesitant to introduce a
different flow in the common altera_edac.c driver, so I followed the
existing architecture where each ECC device has its own Kconfig entry
and corresponding #ifdef blocks in the code.
In terms of savings, this approach mainly avoids compiling code based on
Kconfig selection.
If the preferred approach is to detect and handle the new hardware
without adding a separate Kconfig symbol, I’ll revise the patch accordingly.
In next version, I also need to address Krzysztof’s review comments
regarding the introduction of new ECC device names in the DT bindings.
Thanks,
Nirav
next prev parent reply other threads:[~2025-10-31 11:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 9:22 [PATCH 0/6] Add EDAC support for Agilex5 SoCFPGA niravkumarlaxmidas.rabara
2025-10-28 9:22 ` [PATCH 1/6] dt-bindings: edac: altera: Document additional ECC instances niravkumarlaxmidas.rabara
2025-10-29 6:50 ` Krzysztof Kozlowski
2025-10-31 8:01 ` Niravkumar L Rabara
2025-10-28 9:22 ` [PATCH 2/6] arm64: dts: agilex5: Add ECC manager and submodule nodes niravkumarlaxmidas.rabara
2025-10-29 6:51 ` Krzysztof Kozlowski
2025-10-28 9:22 ` [PATCH 3/6] EDAC/altera: Add DBE interrupt handling for Agilex5 niravkumarlaxmidas.rabara
2025-10-28 9:22 ` [PATCH 4/6] EDAC/altera: Add IO96B ECC support for Agilex5 SoCFPGA niravkumarlaxmidas.rabara
2025-10-30 14:30 ` Borislav Petkov
2025-10-31 11:52 ` Niravkumar L Rabara [this message]
2025-11-02 19:25 ` Borislav Petkov
2025-11-04 3:46 ` kernel test robot
2025-10-28 9:22 ` [PATCH 5/6] EDAC/altera: Add support for CRAM SEU error handling on SoCFPGA niravkumarlaxmidas.rabara
2025-10-29 6:52 ` Krzysztof Kozlowski
2025-10-28 9:22 ` [PATCH 6/6] EDAC: altera: Add ECC support for SDM QSPI on Agilex5 niravkumarlaxmidas.rabara
2025-10-29 6:52 ` Krzysztof Kozlowski
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