From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B03EBC433EF for ; Mon, 18 Apr 2022 10:22:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237672AbiDRKZ1 (ORCPT ); Mon, 18 Apr 2022 06:25:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234883AbiDRKZ0 (ORCPT ); Mon, 18 Apr 2022 06:25:26 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A2F119C16; Mon, 18 Apr 2022 03:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650277367; x=1681813367; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=rB+m8JZE7AYNY8EyI4x/rhw3euV04Ab2K5l6+kXn58I=; b=f62h/yEEz040kksji0abrTocTLjDXGbLwXQY96tdf/TCVroTYQ5Z/CuK 4hCVVMerp3vam7mxpWsx87qPrxul9XPeC49hNsnV+FgiS/y6SZlFcRNuM bTCrfWjtM30U1TCqkdJxwsLK12+uFvSE6k3i4YN7+dM70YbHsguID8epE E=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 18 Apr 2022 03:22:47 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2022 03:22:46 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Apr 2022 03:22:45 -0700 Received: from [10.216.27.177] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Apr 2022 03:22:39 -0700 Message-ID: <24d7180f-dd97-3329-93ad-700bf2dcf0fc@quicinc.com> Date: Mon, 18 Apr 2022 15:52:36 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v12 6/7] pinctrl: qcom: Add SC7280 lpass pin configuration Content-Language: en-US To: Matthias Kaehlcke CC: , , , , , , , , , , , , , , , , Linus Walleij , , Venkata Prasad Potturu , References: <1647447426-23425-1-git-send-email-quic_srivasam@quicinc.com> <1647447426-23425-7-git-send-email-quic_srivasam@quicinc.com> From: Srinivasa Rao Mandadapu Organization: Qualcomm In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 4/16/2022 5:00 AM, Matthias Kaehlcke wrote: Thanks for your time Matthias!!! > On Wed, Mar 16, 2022 at 09:47:05PM +0530, Srinivasa Rao Mandadapu wrote: >> Add pin control support for SC7280 LPASS LPI. >> >> Signed-off-by: Srinivasa Rao Mandadapu >> Co-developed-by: Venkata Prasad Potturu >> Signed-off-by: Venkata Prasad Potturu >> ... >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c >> new file mode 100644 >> index 0000000..d67ff25 >> --- /dev/null >> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c >> >> ... >> +/* sc7280 variant specific data */ > nit: the comment is a bit redundant in a sc7280 specific driver Okay. will remove it. > >> +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = { >> + PINCTRL_PIN(0, "gpio0"), >> + PINCTRL_PIN(1, "gpio1"), >> + PINCTRL_PIN(2, "gpio2"), >> + PINCTRL_PIN(3, "gpio3"), >> + PINCTRL_PIN(4, "gpio4"), >> + PINCTRL_PIN(5, "gpio5"), >> + PINCTRL_PIN(6, "gpio6"), >> + PINCTRL_PIN(7, "gpio7"), >> + PINCTRL_PIN(8, "gpio8"), >> + PINCTRL_PIN(9, "gpio9"), >> + PINCTRL_PIN(10, "gpio10"), >> + PINCTRL_PIN(11, "gpio11"), >> + PINCTRL_PIN(12, "gpio12"), >> + PINCTRL_PIN(13, "gpio13"), >> + PINCTRL_PIN(14, "gpio14"), >> +}; >> + > Reviewed-by: Matthias Kaehlcke