[PATCH 0/8] drm/msm: Introduce display support for SM8650

[PATCH 0/8] drm/msm: Introduce display support for SM8650

[Neil Armstrong]

The SM8650 MDSS is very close from the MDSS 9.0.0 found
on the SM8550 SoC, with the following difference:
- DSI PHY 2.8.8, no significant differences
- DPU 10.0.0:
  - Enhanced max_linewidth to 8k
  - PINGPONG_8 & PINGPONG_9
  - MERGE_3D_4
  - DSC_4 & DSC_5, DSC_NATIVE_42x on DSC0/1

This patchset contains DSI PHY, DSI Controller, DPU & MDSS bindings
in addition to the driver changes.

Support for Display Port output is expected for later.

Dependencies: None

For convenience, a regularly refreshed linux-next based git tree containing
all the SM8650 related work is available at:
https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm85650/upstream/integ

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (8):
      dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY
      dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI Controller
      dt-bindings: display: msm: document the SM8650 DPU
      dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem
      drm/msm: dpu1: add support for SM8650 DPU
      drm/msm: mdss: add support for SM8650
      drm/msm: dsi: add support for DSI-PHY on SM8650
      drm/msm: dsi: add support for DSI 2.8.0

 .../bindings/display/msm/dsi-controller-main.yaml  |   2 +
 .../bindings/display/msm/dsi-phy-7nm.yaml          |   1 +
 .../bindings/display/msm/qcom,sm8650-dpu.yaml      | 127 ++++++
 .../bindings/display/msm/qcom,sm8650-mdss.yaml     | 322 +++++++++++++++
 .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h    | 458 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  23 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c                  |  17 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h                  |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c              |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h              |   1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c          |  27 ++
 drivers/gpu/drm/msm/msm_mdss.c                     |   1 +
 15 files changed, 987 insertions(+)
---
base-commit: fe1998aa935b44ef873193c0772c43bce74f17dc
change-id: 20231016-topic-sm8650-upstream-mdss-e3d95e09c7b8

Best regards,
-- 
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH 1/8] dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY

[Neil Armstrong]

Document the DSI PHY on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index dd6619555a12..7e764eac3ef3 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -22,6 +22,7 @@ properties:
       - qcom,sm8350-dsi-phy-5nm
       - qcom,sm8450-dsi-phy-5nm
       - qcom,sm8550-dsi-phy-4nm
+      - qcom,sm8650-dsi-phy-4nm
 
   reg:
     items:

-- 
2.34.1

Re: [PATCH 1/8] dt-bindings: display: msm-dsi-phy-7nm: document the SM8650 DSI PHY

[Krzysztof Kozlowski]

On 25/10/2023 09:34, Neil Armstrong wrote:
> Document the DSI PHY on the SM8650 Platform.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 2/8] dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI Controller

[Neil Armstrong]

Document the DSI Controller on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index c6dbab65d5f7..24944979d500 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -35,6 +35,7 @@ properties:
               - qcom,sm8350-dsi-ctrl
               - qcom,sm8450-dsi-ctrl
               - qcom,sm8550-dsi-ctrl
+              - qcom,sm8650-dsi-ctrl
           - const: qcom,mdss-dsi-ctrl
       - enum:
           - qcom,dsi-ctrl-6g-qcm2290
@@ -333,6 +334,7 @@ allOf:
               - qcom,sm8350-dsi-ctrl
               - qcom,sm8450-dsi-ctrl
               - qcom,sm8550-dsi-ctrl
+              - qcom,sm8650-dsi-ctrl
     then:
       properties:
         clocks:

-- 
2.34.1

Re: [PATCH 2/8] dt-bindings: display: msm-dsi-controller-main: document the SM8650 DSI Controller

[Krzysztof Kozlowski]

On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the DSI Controller on the SM8650 Platform.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 3/8] dt-bindings: display: msm: document the SM8650 DPU

[Neil Armstrong]

Document the DPU Display Controller on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../bindings/display/msm/qcom,sm8650-dpu.yaml      | 127 +++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
new file mode 100644
index 000000000000..a01d15a03317
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 Display DPU
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sm8650-dpu
+
+  reg:
+    items:
+      - description: Address offset and size for mdp register set
+      - description: Address offset and size for vbif register set
+
+  reg-names:
+    items:
+      - const: mdp
+      - const: vbif
+
+  clocks:
+    items:
+      - description: Display hf axi
+      - description: Display MDSS ahb
+      - description: Display lut
+      - description: Display core
+      - description: Display vsync
+
+  clock-names:
+    items:
+      - const: nrt_bus
+      - const: iface
+      - const: lut
+      - const: core
+      - const: vsync
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-controller@ae01000 {
+        compatible = "qcom,sm8650-dpu";
+        reg = <0x0ae01000 0x8f000>,
+              <0x0aeb0000 0x2008>;
+        reg-names = "mdp", "vbif";
+
+        clocks = <&gcc_axi_clk>,
+                 <&dispcc_ahb_clk>,
+                 <&dispcc_mdp_lut_clk>,
+                 <&dispcc_mdp_clk>,
+                 <&dispcc_vsync_clk>;
+        clock-names = "nrt_bus",
+                      "iface",
+                      "lut",
+                      "core",
+                      "vsync";
+
+        assigned-clocks = <&dispcc_vsync_clk>;
+        assigned-clock-rates = <19200000>;
+
+        operating-points-v2 = <&mdp_opp_table>;
+        power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dpu_intf1_out: endpoint {
+                    remote-endpoint = <&dsi0_in>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dpu_intf2_out: endpoint {
+                    remote-endpoint = <&dsi1_in>;
+                };
+            };
+        };
+
+        mdp_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-200000000 {
+                opp-hz = /bits/ 64 <200000000>;
+                required-opps = <&rpmhpd_opp_low_svs>;
+            };
+
+            opp-325000000 {
+                opp-hz = /bits/ 64 <325000000>;
+                required-opps = <&rpmhpd_opp_svs>;
+            };
+
+            opp-375000000 {
+                opp-hz = /bits/ 64 <375000000>;
+                required-opps = <&rpmhpd_opp_svs_l1>;
+            };
+
+            opp-514000000 {
+                opp-hz = /bits/ 64 <514000000>;
+                required-opps = <&rpmhpd_opp_nom>;
+            };
+        };
+    };
+...

-- 
2.34.1

Re: [PATCH 3/8] dt-bindings: display: msm: document the SM8650 DPU

[Krzysztof Kozlowski]

On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the DPU Display Controller on the SM8650 Platform.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 4/8] dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem

[Neil Armstrong]

Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../bindings/display/msm/qcom,sm8650-mdss.yaml     | 322 +++++++++++++++++++++
 1 file changed, 322 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml
new file mode 100644
index 000000000000..5638c1ea692e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml
@@ -0,0 +1,322 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 Display MDSS
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+description:
+  SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+  DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sm8650-mdss
+
+  clocks:
+    items:
+      - description: Display AHB
+      - description: Display hf AXI
+      - description: Display core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    properties:
+      compatible:
+        const: qcom,sm8650-dpu
+
+  "^dsi@[0-9a-f]+$":
+    type: object
+    properties:
+      compatible:
+        items:
+          - const: qcom,sm8650-dsi-ctrl
+          - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    properties:
+      compatible:
+        const: qcom,sm8650-dsi-phy-4nm
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-subsystem@ae00000 {
+        compatible = "qcom,sm8650-mdss";
+        reg = <0x0ae00000 0x1000>;
+        reg-names = "mdss";
+
+        resets = <&dispcc_core_bcr>;
+
+        power-domains = <&dispcc_gdsc>;
+
+        clocks = <&gcc_ahb_clk>,
+                 <&gcc_axi_clk>,
+                 <&dispcc_mdp_clk>;
+        clock-names = "bus", "nrt_bus", "core";
+
+        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        iommus = <&apps_smmu 0x1c00 0x2>;
+
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        display-controller@ae01000 {
+            compatible = "qcom,sm8650-dpu";
+            reg = <0x0ae01000 0x8f000>,
+                  <0x0aeb0000 0x2008>;
+            reg-names = "mdp", "vbif";
+
+            clocks = <&gcc_axi_clk>,
+                     <&dispcc_ahb_clk>,
+                     <&dispcc_mdp_lut_clk>,
+                     <&dispcc_mdp_clk>,
+                     <&dispcc_mdp_vsync_clk>;
+            clock-names = "nrt_bus",
+                          "iface",
+                          "lut",
+                          "core",
+                          "vsync";
+
+            assigned-clocks = <&dispcc_mdp_vsync_clk>;
+            assigned-clock-rates = <19200000>;
+
+            operating-points-v2 = <&mdp_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+            interrupt-parent = <&mdss>;
+            interrupts = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    dpu_intf1_out: endpoint {
+                        remote-endpoint = <&dsi0_in>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    dpu_intf2_out: endpoint {
+                        remote-endpoint = <&dsi1_in>;
+                    };
+                };
+            };
+
+            mdp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-200000000 {
+                    opp-hz = /bits/ 64 <200000000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-325000000 {
+                    opp-hz = /bits/ 64 <325000000>;
+                    required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-375000000 {
+                    opp-hz = /bits/ 64 <375000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+
+                opp-514000000 {
+                    opp-hz = /bits/ 64 <514000000>;
+                    required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+
+        dsi@ae94000 {
+            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+            reg = <0x0ae94000 0x400>;
+            reg-names = "dsi_ctrl";
+
+            interrupt-parent = <&mdss>;
+            interrupts = <4>;
+
+            clocks = <&dispc_byte_clk>,
+                     <&dispcc_intf_clk>,
+                     <&dispcc_pclk>,
+                     <&dispcc_esc_clk>,
+                     <&dispcc_ahb_clk>,
+                     <&gcc_bus_clk>;
+            clock-names = "byte",
+                          "byte_intf",
+                          "pixel",
+                          "core",
+                          "iface",
+                          "bus";
+
+            assigned-clocks = <&dispcc_byte_clk>,
+                              <&dispcc_pclk>;
+            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+            operating-points-v2 = <&dsi_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+            phys = <&dsi0_phy>;
+            phy-names = "dsi";
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    dsi0_in: endpoint {
+                        remote-endpoint = <&dpu_intf1_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    dsi0_out: endpoint {
+                    };
+                };
+            };
+
+            dsi_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-187500000 {
+                    opp-hz = /bits/ 64 <187500000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-300000000 {
+                    opp-hz = /bits/ 64 <300000000>;
+                    required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-358000000 {
+                    opp-hz = /bits/ 64 <358000000>;
+                    required-opps = <&rpmhpd_opp_svs_l1>;
+                };
+            };
+        };
+
+        dsi0_phy: phy@ae94400 {
+            compatible = "qcom,sm8650-dsi-phy-4nm";
+            reg = <0x0ae95000 0x200>,
+                  <0x0ae95200 0x280>,
+                  <0x0ae95500 0x400>;
+            reg-names = "dsi_phy",
+                        "dsi_phy_lane",
+                        "dsi_pll";
+
+            #clock-cells = <1>;
+            #phy-cells = <0>;
+
+            clocks = <&dispcc_iface_clk>,
+                     <&rpmhcc_ref_clk>;
+            clock-names = "iface", "ref";
+        };
+
+        dsi@ae96000 {
+            compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+            reg = <0x0ae96000 0x400>;
+            reg-names = "dsi_ctrl";
+
+            interrupt-parent = <&mdss>;
+            interrupts = <5>;
+
+            clocks = <&dispc_byte_clk>,
+                     <&dispcc_intf_clk>,
+                     <&dispcc_pclk>,
+                     <&dispcc_esc_clk>,
+                     <&dispcc_ahb_clk>,
+                     <&gcc_bus_clk>;
+            clock-names = "byte",
+                          "byte_intf",
+                          "pixel",
+                          "core",
+                          "iface",
+                          "bus";
+
+            assigned-clocks = <&dispcc_byte_clk>,
+                              <&dispcc_pclk>;
+            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+            operating-points-v2 = <&dsi_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+            phys = <&dsi1_phy>;
+            phy-names = "dsi";
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    dsi1_in: endpoint {
+                        remote-endpoint = <&dpu_intf2_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    dsi1_out: endpoint {
+                    };
+                };
+            };
+        };
+
+        dsi1_phy: phy@ae96400 {
+            compatible = "qcom,sm8650-dsi-phy-4nm";
+            reg = <0x0ae97000 0x200>,
+                  <0x0ae97200 0x280>,
+                  <0x0ae97500 0x400>;
+            reg-names = "dsi_phy",
+                        "dsi_phy_lane",
+                        "dsi_pll";
+
+            #clock-cells = <1>;
+            #phy-cells = <0>;
+
+            clocks = <&dispcc_iface_clk>,
+                     <&rpmhcc_ref_clk>;
+            clock-names = "iface", "ref";
+        };
+    };
+...

-- 
2.34.1

Re: [PATCH 4/8] dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem

[Krzysztof Kozlowski]

On 25/10/2023 09:35, Neil Armstrong wrote:
> Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  .../bindings/display/msm/qcom,sm8650-mdss.yaml     | 322 +++++++++++++++++++++
>  1 file changed, 322 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 5/8] drm/msm: dpu1: add support for SM8650 DPU

[Neil Armstrong]

Add DPU version 10.0 support for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h    | 458 +++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  23 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
 5 files changed, 486 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
new file mode 100644
index 000000000000..3a37d78804e7
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -0,0 +1,458 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_10_0_SM8650_H
+#define _DPU_10_0_SM8650_H
+
+static const struct dpu_caps sm8650_dpu_caps = {
+	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+	.max_mixer_blendstages = 0xb,
+	.qseed_type = DPU_SSPP_SCALER_QSEED4,
+	.has_src_split = true,
+	.has_dim_layer = true,
+	.has_idle_pc = true,
+	.has_3d_merge = true,
+	.max_linewidth = 8192,
+	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sm8650_mdp = {
+	.name = "top_0",
+	.base = 0, .len = 0x494,
+	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+	.clk_ctrls = {
+		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+	},
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
+static const struct dpu_ctl_cfg sm8650_ctl[] = {
+	{
+		.name = "ctl_0", .id = CTL_0,
+		.base = 0x15000, .len = 0x1000,
+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+	}, {
+		.name = "ctl_1", .id = CTL_1,
+		.base = 0x16000, .len = 0x1000,
+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+	}, {
+		.name = "ctl_2", .id = CTL_2,
+		.base = 0x17000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+	}, {
+		.name = "ctl_3", .id = CTL_3,
+		.base = 0x18000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+	}, {
+		.name = "ctl_4", .id = CTL_4,
+		.base = 0x19000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+	}, {
+		.name = "ctl_5", .id = CTL_5,
+		.base = 0x1a000, .len = 0x1000,
+		.features = CTL_SM8550_MASK,
+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+	},
+};
+
+static const struct dpu_sspp_cfg sm8650_sspp[] = {
+	{
+		.name = "sspp_0", .id = SSPP_VIG0,
+		.base = 0x4000, .len = 0x344,
+		.features = VIG_SC7180_MASK,
+		.sblk = &sm8550_vig_sblk_0,
+		.xin_id = 0,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_1", .id = SSPP_VIG1,
+		.base = 0x6000, .len = 0x344,
+		.features = VIG_SC7180_MASK,
+		.sblk = &sm8550_vig_sblk_1,
+		.xin_id = 4,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_2", .id = SSPP_VIG2,
+		.base = 0x8000, .len = 0x344,
+		.features = VIG_SC7180_MASK,
+		.sblk = &sm8550_vig_sblk_2,
+		.xin_id = 8,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_3", .id = SSPP_VIG3,
+		.base = 0xa000, .len = 0x344,
+		.features = VIG_SC7180_MASK,
+		.sblk = &sm8550_vig_sblk_3,
+		.xin_id = 12,
+		.type = SSPP_TYPE_VIG,
+	}, {
+		.name = "sspp_8", .id = SSPP_DMA0,
+		.base = 0x24000, .len = 0x344,
+		.features = DMA_SDM845_MASK,
+		.sblk = &sdm845_dma_sblk_0,
+		.xin_id = 1,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_9", .id = SSPP_DMA1,
+		.base = 0x26000, .len = 0x344,
+		.features = DMA_SDM845_MASK,
+		.sblk = &sdm845_dma_sblk_1,
+		.xin_id = 5,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_10", .id = SSPP_DMA2,
+		.base = 0x28000, .len = 0x344,
+		.features = DMA_SDM845_MASK,
+		.sblk = &sdm845_dma_sblk_2,
+		.xin_id = 9,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_11", .id = SSPP_DMA3,
+		.base = 0x2a000, .len = 0x344,
+		.features = DMA_SDM845_MASK,
+		.sblk = &sdm845_dma_sblk_3,
+		.xin_id = 13,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_12", .id = SSPP_DMA4,
+		.base = 0x2c000, .len = 0x344,
+		.features = DMA_CURSOR_SDM845_MASK,
+		.sblk = &sm8550_dma_sblk_4,
+		.xin_id = 14,
+		.type = SSPP_TYPE_DMA,
+	}, {
+		.name = "sspp_13", .id = SSPP_DMA5,
+		.base = 0x2e000, .len = 0x344,
+		.features = DMA_CURSOR_SDM845_MASK,
+		.sblk = &sm8550_dma_sblk_5,
+		.xin_id = 15,
+		.type = SSPP_TYPE_DMA,
+	},
+};
+
+static const struct dpu_lm_cfg sm8650_lm[] = {
+	{
+		.name = "lm_0", .id = LM_0,
+		.base = 0x44000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_1,
+		.pingpong = PINGPONG_0,
+		.dspp = DSPP_0,
+	}, {
+		.name = "lm_1", .id = LM_1,
+		.base = 0x45000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_0,
+		.pingpong = PINGPONG_1,
+		.dspp = DSPP_1,
+	}, {
+		.name = "lm_2", .id = LM_2,
+		.base = 0x46000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_3,
+		.pingpong = PINGPONG_2,
+	}, {
+		.name = "lm_3", .id = LM_3,
+		.base = 0x47000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_2,
+		.pingpong = PINGPONG_3,
+	}, {
+		.name = "lm_4", .id = LM_4,
+		.base = 0x48000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_5,
+		.pingpong = PINGPONG_4,
+	}, {
+		.name = "lm_5", .id = LM_5,
+		.base = 0x49000, .len = 0x400,
+		.features = MIXER_SDM845_MASK,
+		.sblk = &sdm845_lm_sblk,
+		.lm_pair = LM_4,
+		.pingpong = PINGPONG_5,
+	},
+};
+
+static const struct dpu_dspp_cfg sm8650_dspp[] = {
+	{
+		.name = "dspp_0", .id = DSPP_0,
+		.base = 0x54000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sdm845_dspp_sblk,
+	}, {
+		.name = "dspp_1", .id = DSPP_1,
+		.base = 0x56000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sdm845_dspp_sblk,
+	}, {
+		.name = "dspp_2", .id = DSPP_2,
+		.base = 0x58000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sdm845_dspp_sblk,
+	}, {
+		.name = "dspp_3", .id = DSPP_3,
+		.base = 0x5a000, .len = 0x1800,
+		.features = DSPP_SC7180_MASK,
+		.sblk = &sdm845_dspp_sblk,
+	},
+};
+
+static const struct dpu_pingpong_cfg sm8650_pp[] = {
+	{
+		.name = "pingpong_0", .id = PINGPONG_0,
+		.base = 0x69000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_0,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+	}, {
+		.name = "pingpong_1", .id = PINGPONG_1,
+		.base = 0x6a000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_0,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+	}, {
+		.name = "pingpong_2", .id = PINGPONG_2,
+		.base = 0x6b000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_1,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+	}, {
+		.name = "pingpong_3", .id = PINGPONG_3,
+		.base = 0x6c000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_1,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+	}, {
+		.name = "pingpong_4", .id = PINGPONG_4,
+		.base = 0x6d000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_2,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+	}, {
+		.name = "pingpong_5", .id = PINGPONG_5,
+		.base = 0x6e000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_2,
+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+	}, {
+		.name = "pingpong_6", .id = PINGPONG_6,
+		.base = 0x66000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_3,
+	}, {
+		.name = "pingpong_7", .id = PINGPONG_7,
+		.base = 0x66400, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_3,
+	}, {
+		.name = "pingpong_8", .id = PINGPONG_8,
+		.base = 0x7e000, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_4,
+	}, {
+		.name = "pingpong_9", .id = PINGPONG_9,
+		.base = 0x7e400, .len = 0,
+		.features = BIT(DPU_PINGPONG_DITHER),
+		.sblk = &sc7280_pp_sblk,
+		.merge_3d = MERGE_3D_4,
+	},
+};
+
+static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = {
+	{
+		.name = "merge_3d_0", .id = MERGE_3D_0,
+		.base = 0x4e000, .len = 0x8,
+	}, {
+		.name = "merge_3d_1", .id = MERGE_3D_1,
+		.base = 0x4f000, .len = 0x8,
+	}, {
+		.name = "merge_3d_2", .id = MERGE_3D_2,
+		.base = 0x50000, .len = 0x8,
+	}, {
+		.name = "merge_3d_3", .id = MERGE_3D_3,
+		.base = 0x66700, .len = 0x8,
+	}, {
+		.name = "merge_3d_4", .id = MERGE_3D_4,
+		.base = 0x7e700, .len = 0x8,
+	},
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg sm8650_dsc[] = {
+	{
+		.name = "dce_0_0", .id = DSC_0,
+		.base = 0x80000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &dsc_sblk_0,
+	}, {
+		.name = "dce_0_1", .id = DSC_1,
+		.base = 0x80000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &dsc_sblk_1,
+	}, {
+		.name = "dce_1_0", .id = DSC_2,
+		.base = 0x81000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &dsc_sblk_0,
+	}, {
+		.name = "dce_1_1", .id = DSC_3,
+		.base = 0x81000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+		.sblk = &dsc_sblk_1,
+	}, {
+		.name = "dce_2_0", .id = DSC_4,
+		.base = 0x82000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2),
+		.sblk = &dsc_sblk_0,
+	}, {
+		.name = "dce_2_1", .id = DSC_5,
+		.base = 0x82000, .len = 0x6,
+		.features = BIT(DPU_DSC_HW_REV_1_2),
+		.sblk = &dsc_sblk_1,
+	},
+};
+
+static const struct dpu_wb_cfg sm8650_wb[] = {
+	{
+		.name = "wb_2", .id = WB_2,
+		.base = 0x65000, .len = 0x2c8,
+		.features = WB_SM8250_MASK,
+		.format_list = wb2_formats,
+		.num_formats = ARRAY_SIZE(wb2_formats),
+		.xin_id = 6,
+		.vbif_idx = VBIF_RT,
+		.maxlinewidth = 4096,
+		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+	},
+};
+
+static const struct dpu_intf_cfg sm8650_intf[] = {
+	{
+		.name = "intf_0", .id = INTF_0,
+		.base = 0x34000, .len = 0x280,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+	}, {
+		.name = "intf_1", .id = INTF_1,
+		.base = 0x35000, .len = 0x300,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DSI,
+		.controller_id = MSM_DSI_CONTROLLER_0,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+	}, {
+		.name = "intf_2", .id = INTF_2,
+		.base = 0x36000, .len = 0x300,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DSI,
+		.controller_id = MSM_DSI_CONTROLLER_1,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+	}, {
+		.name = "intf_3", .id = INTF_3,
+		.base = 0x37000, .len = 0x280,
+		.features = INTF_SC7280_MASK,
+		.type = INTF_DP,
+		.controller_id = MSM_DP_CONTROLLER_1,
+		.prog_fetch_lines_worst_case = 24,
+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+	},
+};
+
+static const struct dpu_perf_cfg sm8650_perf_data = {
+	.max_bw_low = 17000000,
+	.max_bw_high = 27000000,
+	.min_core_ib = 2500000,
+	.min_llcc_ib = 0,
+	.min_dram_ib = 800000,
+	.min_prefill_lines = 35,
+	/* FIXME: lut tables */
+	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+	.qos_lut_tbl = {
+		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
+		.entries = sc7180_qos_linear
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+		.entries = sc7180_qos_macrotile
+		},
+		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+		.entries = sc7180_qos_nrt
+		},
+		/* TODO: macrotile-qseed is different from macrotile */
+	},
+	.cdp_cfg = {
+		{.rd_enable = 1, .wr_enable = 1},
+		{.rd_enable = 1, .wr_enable = 0}
+	},
+	.clk_inefficiency_factor = 105,
+	.bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version sm8650_mdss_ver = {
+	.core_major_ver = 10,
+	.core_minor_ver = 0,
+};
+
+const struct dpu_mdss_cfg dpu_sm8650_cfg = {
+	.mdss_ver = &sm8650_mdss_ver,
+	.caps = &sm8650_dpu_caps,
+	.mdp = &sm8650_mdp,
+	.ctl_count = ARRAY_SIZE(sm8650_ctl),
+	.ctl = sm8650_ctl,
+	.sspp_count = ARRAY_SIZE(sm8650_sspp),
+	.sspp = sm8650_sspp,
+	.mixer_count = ARRAY_SIZE(sm8650_lm),
+	.mixer = sm8650_lm,
+	.dspp_count = ARRAY_SIZE(sm8650_dspp),
+	.dspp = sm8650_dspp,
+	.pingpong_count = ARRAY_SIZE(sm8650_pp),
+	.pingpong = sm8650_pp,
+	.dsc_count = ARRAY_SIZE(sm8650_dsc),
+	.dsc = sm8650_dsc,
+	.merge_3d_count = ARRAY_SIZE(sm8650_merge_3d),
+	.merge_3d = sm8650_merge_3d,
+	.wb_count = ARRAY_SIZE(sm8650_wb),
+	.wb = sm8650_wb,
+	.intf_count = ARRAY_SIZE(sm8650_intf),
+	.intf = sm8650_intf,
+	.vbif_count = ARRAY_SIZE(sm8650_vbif),
+	.vbif = sm8650_vbif,
+	.perf = &sm8650_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a1aada630780..0b8af44e12dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -472,6 +472,7 @@ static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
+static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 6};
 
 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
 	{
@@ -558,6 +559,26 @@ static const struct dpu_vbif_cfg sm8550_vbif[] = {
 	},
 };
 
+static const struct dpu_vbif_cfg sm8650_vbif[] = {
+	{
+	.name = "vbif_rt", .id = VBIF_RT,
+	.base = 0, .len = 0x1074,
+	.features = BIT(DPU_VBIF_QOS_REMAP),
+	.xin_halt_timeout = 0x4000,
+	.qos_rp_remap_size = 0x40,
+	.qos_rt_tbl = {
+		.npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),
+		.priority_lvl = sm8650_rt_pri_lvl,
+		},
+	.qos_nrt_tbl = {
+		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+		.priority_lvl = sdm845_nrt_pri_lvl,
+		},
+	.memtype_count = 16,
+	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+	},
+};
+
 /*************************************************************
  * PERF data config
  *************************************************************/
@@ -673,3 +694,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
 #include "catalog/dpu_8_1_sm8450.h"
 
 #include "catalog/dpu_9_0_sm8550.h"
+
+#include "catalog/dpu_10_0_sm8650.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index df024e10d3a3..92cce867a7e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -841,5 +841,6 @@ extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
 extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
 extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
+extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
 
 #endif /* _DPU_HW_CATALOG_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index d85157acfbf8..a6702b2bfc68 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -195,6 +195,8 @@ enum dpu_pingpong {
 	PINGPONG_5,
 	PINGPONG_6,
 	PINGPONG_7,
+	PINGPONG_8,
+	PINGPONG_9,
 	PINGPONG_S0,
 	PINGPONG_MAX
 };
@@ -204,6 +206,7 @@ enum dpu_merge_3d {
 	MERGE_3D_1,
 	MERGE_3D_2,
 	MERGE_3D_3,
+	MERGE_3D_4,
 	MERGE_3D_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe7267b3bff5..4a017064207f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1363,6 +1363,7 @@ static const struct of_device_id dpu_dt_match[] = {
 	{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
 	{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
 	{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
+	{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dpu_dt_match);

-- 
2.34.1

Re: [PATCH 5/8] drm/msm: dpu1: add support for SM8650 DPU

[Dmitry Baryshkov]

On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Add DPU version 10.0 support for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks for your patch. Could you please rebase it on top of
https://patchwork.freedesktop.org/series/119804/ ?

> ---
>  .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h    | 458 +++++++++++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  23 ++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   3 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>  5 files changed, 486 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> new file mode 100644
> index 000000000000..3a37d78804e7
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -0,0 +1,458 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DPU_10_0_SM8650_H
> +#define _DPU_10_0_SM8650_H
> +
> +static const struct dpu_caps sm8650_dpu_caps = {
> +       .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> +       .max_mixer_blendstages = 0xb,
> +       .qseed_type = DPU_SSPP_SCALER_QSEED4,
> +       .has_src_split = true,
> +       .has_dim_layer = true,
> +       .has_idle_pc = true,
> +       .has_3d_merge = true,
> +       .max_linewidth = 8192,
> +       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +};
> +
> +static const struct dpu_mdp_cfg sm8650_mdp = {
> +       .name = "top_0",
> +       .base = 0, .len = 0x494,
> +       .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> +       .clk_ctrls = {
> +               [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> +       },
> +};
> +
> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
> +static const struct dpu_ctl_cfg sm8650_ctl[] = {
> +       {
> +               .name = "ctl_0", .id = CTL_0,
> +               .base = 0x15000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> +       }, {
> +               .name = "ctl_1", .id = CTL_1,
> +               .base = 0x16000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> +       }, {
> +               .name = "ctl_2", .id = CTL_2,
> +               .base = 0x17000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK,
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> +       }, {
> +               .name = "ctl_3", .id = CTL_3,
> +               .base = 0x18000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK,
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> +       }, {
> +               .name = "ctl_4", .id = CTL_4,
> +               .base = 0x19000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK,
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> +       }, {
> +               .name = "ctl_5", .id = CTL_5,
> +               .base = 0x1a000, .len = 0x1000,
> +               .features = CTL_SM8550_MASK,
> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> +       },
> +};
> +
> +static const struct dpu_sspp_cfg sm8650_sspp[] = {
> +       {
> +               .name = "sspp_0", .id = SSPP_VIG0,
> +               .base = 0x4000, .len = 0x344,
> +               .features = VIG_SC7180_MASK,

Could you please use _SDMA mask here after testing that SmartDMA works
as expected?

> +               .sblk = &sm8550_vig_sblk_0,
> +               .xin_id = 0,
> +               .type = SSPP_TYPE_VIG,
> +       }, {
> +               .name = "sspp_1", .id = SSPP_VIG1,
> +               .base = 0x6000, .len = 0x344,
> +               .features = VIG_SC7180_MASK,
> +               .sblk = &sm8550_vig_sblk_1,
> +               .xin_id = 4,
> +               .type = SSPP_TYPE_VIG,
> +       }, {
> +               .name = "sspp_2", .id = SSPP_VIG2,
> +               .base = 0x8000, .len = 0x344,
> +               .features = VIG_SC7180_MASK,
> +               .sblk = &sm8550_vig_sblk_2,
> +               .xin_id = 8,
> +               .type = SSPP_TYPE_VIG,
> +       }, {
> +               .name = "sspp_3", .id = SSPP_VIG3,
> +               .base = 0xa000, .len = 0x344,
> +               .features = VIG_SC7180_MASK,
> +               .sblk = &sm8550_vig_sblk_3,
> +               .xin_id = 12,
> +               .type = SSPP_TYPE_VIG,
> +       }, {
> +               .name = "sspp_8", .id = SSPP_DMA0,
> +               .base = 0x24000, .len = 0x344,
> +               .features = DMA_SDM845_MASK,
> +               .sblk = &sdm845_dma_sblk_0,
> +               .xin_id = 1,
> +               .type = SSPP_TYPE_DMA,
> +       }, {
> +               .name = "sspp_9", .id = SSPP_DMA1,
> +               .base = 0x26000, .len = 0x344,
> +               .features = DMA_SDM845_MASK,
> +               .sblk = &sdm845_dma_sblk_1,
> +               .xin_id = 5,
> +               .type = SSPP_TYPE_DMA,
> +       }, {
> +               .name = "sspp_10", .id = SSPP_DMA2,
> +               .base = 0x28000, .len = 0x344,
> +               .features = DMA_SDM845_MASK,
> +               .sblk = &sdm845_dma_sblk_2,
> +               .xin_id = 9,
> +               .type = SSPP_TYPE_DMA,
> +       }, {
> +               .name = "sspp_11", .id = SSPP_DMA3,
> +               .base = 0x2a000, .len = 0x344,
> +               .features = DMA_SDM845_MASK,
> +               .sblk = &sdm845_dma_sblk_3,
> +               .xin_id = 13,
> +               .type = SSPP_TYPE_DMA,
> +       }, {
> +               .name = "sspp_12", .id = SSPP_DMA4,
> +               .base = 0x2c000, .len = 0x344,
> +               .features = DMA_CURSOR_SDM845_MASK,
> +               .sblk = &sm8550_dma_sblk_4,
> +               .xin_id = 14,
> +               .type = SSPP_TYPE_DMA,
> +       }, {
> +               .name = "sspp_13", .id = SSPP_DMA5,
> +               .base = 0x2e000, .len = 0x344,
> +               .features = DMA_CURSOR_SDM845_MASK,
> +               .sblk = &sm8550_dma_sblk_5,
> +               .xin_id = 15,
> +               .type = SSPP_TYPE_DMA,
> +       },
> +};
> +
> +static const struct dpu_lm_cfg sm8650_lm[] = {
> +       {
> +               .name = "lm_0", .id = LM_0,
> +               .base = 0x44000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_1,
> +               .pingpong = PINGPONG_0,
> +               .dspp = DSPP_0,
> +       }, {
> +               .name = "lm_1", .id = LM_1,
> +               .base = 0x45000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_0,
> +               .pingpong = PINGPONG_1,
> +               .dspp = DSPP_1,
> +       }, {
> +               .name = "lm_2", .id = LM_2,
> +               .base = 0x46000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_3,
> +               .pingpong = PINGPONG_2,
> +       }, {
> +               .name = "lm_3", .id = LM_3,
> +               .base = 0x47000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_2,
> +               .pingpong = PINGPONG_3,
> +       }, {
> +               .name = "lm_4", .id = LM_4,
> +               .base = 0x48000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_5,
> +               .pingpong = PINGPONG_4,
> +       }, {
> +               .name = "lm_5", .id = LM_5,
> +               .base = 0x49000, .len = 0x400,
> +               .features = MIXER_SDM845_MASK,
> +               .sblk = &sdm845_lm_sblk,
> +               .lm_pair = LM_4,
> +               .pingpong = PINGPONG_5,
> +       },
> +};
> +
> +static const struct dpu_dspp_cfg sm8650_dspp[] = {
> +       {
> +               .name = "dspp_0", .id = DSPP_0,
> +               .base = 0x54000, .len = 0x1800,
> +               .features = DSPP_SC7180_MASK,
> +               .sblk = &sdm845_dspp_sblk,
> +       }, {
> +               .name = "dspp_1", .id = DSPP_1,
> +               .base = 0x56000, .len = 0x1800,
> +               .features = DSPP_SC7180_MASK,
> +               .sblk = &sdm845_dspp_sblk,
> +       }, {
> +               .name = "dspp_2", .id = DSPP_2,
> +               .base = 0x58000, .len = 0x1800,
> +               .features = DSPP_SC7180_MASK,
> +               .sblk = &sdm845_dspp_sblk,
> +       }, {
> +               .name = "dspp_3", .id = DSPP_3,
> +               .base = 0x5a000, .len = 0x1800,
> +               .features = DSPP_SC7180_MASK,
> +               .sblk = &sdm845_dspp_sblk,
> +       },
> +};
> +
> +static const struct dpu_pingpong_cfg sm8650_pp[] = {
> +       {
> +               .name = "pingpong_0", .id = PINGPONG_0,
> +               .base = 0x69000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_0,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> +       }, {
> +               .name = "pingpong_1", .id = PINGPONG_1,
> +               .base = 0x6a000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_0,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> +       }, {
> +               .name = "pingpong_2", .id = PINGPONG_2,
> +               .base = 0x6b000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_1,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> +       }, {
> +               .name = "pingpong_3", .id = PINGPONG_3,
> +               .base = 0x6c000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_1,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> +       }, {
> +               .name = "pingpong_4", .id = PINGPONG_4,
> +               .base = 0x6d000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_2,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> +       }, {
> +               .name = "pingpong_5", .id = PINGPONG_5,
> +               .base = 0x6e000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_2,
> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> +       }, {
> +               .name = "pingpong_6", .id = PINGPONG_6,
> +               .base = 0x66000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_3,
> +       }, {
> +               .name = "pingpong_7", .id = PINGPONG_7,
> +               .base = 0x66400, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_3,
> +       }, {
> +               .name = "pingpong_8", .id = PINGPONG_8,
> +               .base = 0x7e000, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_4,
> +       }, {
> +               .name = "pingpong_9", .id = PINGPONG_9,
> +               .base = 0x7e400, .len = 0,
> +               .features = BIT(DPU_PINGPONG_DITHER),
> +               .sblk = &sc7280_pp_sblk,
> +               .merge_3d = MERGE_3D_4,
> +       },
> +};
> +
> +static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = {
> +       {
> +               .name = "merge_3d_0", .id = MERGE_3D_0,
> +               .base = 0x4e000, .len = 0x8,
> +       }, {
> +               .name = "merge_3d_1", .id = MERGE_3D_1,
> +               .base = 0x4f000, .len = 0x8,
> +       }, {
> +               .name = "merge_3d_2", .id = MERGE_3D_2,
> +               .base = 0x50000, .len = 0x8,
> +       }, {
> +               .name = "merge_3d_3", .id = MERGE_3D_3,
> +               .base = 0x66700, .len = 0x8,
> +       }, {
> +               .name = "merge_3d_4", .id = MERGE_3D_4,
> +               .base = 0x7e700, .len = 0x8,
> +       },
> +};
> +
> +/*
> + * NOTE: Each display compression engine (DCE) contains dual hard
> + * slice DSC encoders so both share same base address but with
> + * its own different sub block address.
> + */
> +static const struct dpu_dsc_cfg sm8650_dsc[] = {
> +       {
> +               .name = "dce_0_0", .id = DSC_0,
> +               .base = 0x80000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +               .sblk = &dsc_sblk_0,
> +       }, {
> +               .name = "dce_0_1", .id = DSC_1,
> +               .base = 0x80000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +               .sblk = &dsc_sblk_1,
> +       }, {
> +               .name = "dce_1_0", .id = DSC_2,
> +               .base = 0x81000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +               .sblk = &dsc_sblk_0,
> +       }, {
> +               .name = "dce_1_1", .id = DSC_3,
> +               .base = 0x81000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> +               .sblk = &dsc_sblk_1,
> +       }, {
> +               .name = "dce_2_0", .id = DSC_4,
> +               .base = 0x82000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2),
> +               .sblk = &dsc_sblk_0,
> +       }, {
> +               .name = "dce_2_1", .id = DSC_5,
> +               .base = 0x82000, .len = 0x6,
> +               .features = BIT(DPU_DSC_HW_REV_1_2),
> +               .sblk = &dsc_sblk_1,
> +       },
> +};
> +
> +static const struct dpu_wb_cfg sm8650_wb[] = {
> +       {
> +               .name = "wb_2", .id = WB_2,
> +               .base = 0x65000, .len = 0x2c8,
> +               .features = WB_SM8250_MASK,
> +               .format_list = wb2_formats,
> +               .num_formats = ARRAY_SIZE(wb2_formats),
> +               .xin_id = 6,
> +               .vbif_idx = VBIF_RT,
> +               .maxlinewidth = 4096,
> +               .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
> +       },
> +};
> +
> +static const struct dpu_intf_cfg sm8650_intf[] = {
> +       {
> +               .name = "intf_0", .id = INTF_0,
> +               .base = 0x34000, .len = 0x280,
> +               .features = INTF_SC7280_MASK,
> +               .type = INTF_DP,
> +               .controller_id = MSM_DP_CONTROLLER_0,
> +               .prog_fetch_lines_worst_case = 24,
> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> +       }, {
> +               .name = "intf_1", .id = INTF_1,
> +               .base = 0x35000, .len = 0x300,
> +               .features = INTF_SC7280_MASK,
> +               .type = INTF_DSI,
> +               .controller_id = MSM_DSI_CONTROLLER_0,
> +               .prog_fetch_lines_worst_case = 24,
> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> +               .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
> +       }, {
> +               .name = "intf_2", .id = INTF_2,
> +               .base = 0x36000, .len = 0x300,
> +               .features = INTF_SC7280_MASK,
> +               .type = INTF_DSI,
> +               .controller_id = MSM_DSI_CONTROLLER_1,
> +               .prog_fetch_lines_worst_case = 24,
> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> +               .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
> +       }, {
> +               .name = "intf_3", .id = INTF_3,
> +               .base = 0x37000, .len = 0x280,
> +               .features = INTF_SC7280_MASK,
> +               .type = INTF_DP,
> +               .controller_id = MSM_DP_CONTROLLER_1,
> +               .prog_fetch_lines_worst_case = 24,
> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> +       },
> +};
> +
> +static const struct dpu_perf_cfg sm8650_perf_data = {
> +       .max_bw_low = 17000000,
> +       .max_bw_high = 27000000,
> +       .min_core_ib = 2500000,
> +       .min_llcc_ib = 0,
> +       .min_dram_ib = 800000,
> +       .min_prefill_lines = 35,
> +       /* FIXME: lut tables */
> +       .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
> +       .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
> +       .qos_lut_tbl = {
> +               {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> +               .entries = sc7180_qos_linear
> +               },
> +               {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
> +               .entries = sc7180_qos_macrotile
> +               },
> +               {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
> +               .entries = sc7180_qos_nrt
> +               },
> +               /* TODO: macrotile-qseed is different from macrotile */
> +       },
> +       .cdp_cfg = {
> +               {.rd_enable = 1, .wr_enable = 1},
> +               {.rd_enable = 1, .wr_enable = 0}
> +       },
> +       .clk_inefficiency_factor = 105,
> +       .bw_inefficiency_factor = 120,
> +};
> +
> +static const struct dpu_mdss_version sm8650_mdss_ver = {
> +       .core_major_ver = 10,
> +       .core_minor_ver = 0,
> +};
> +
> +const struct dpu_mdss_cfg dpu_sm8650_cfg = {
> +       .mdss_ver = &sm8650_mdss_ver,
> +       .caps = &sm8650_dpu_caps,
> +       .mdp = &sm8650_mdp,
> +       .ctl_count = ARRAY_SIZE(sm8650_ctl),
> +       .ctl = sm8650_ctl,
> +       .sspp_count = ARRAY_SIZE(sm8650_sspp),
> +       .sspp = sm8650_sspp,
> +       .mixer_count = ARRAY_SIZE(sm8650_lm),
> +       .mixer = sm8650_lm,
> +       .dspp_count = ARRAY_SIZE(sm8650_dspp),
> +       .dspp = sm8650_dspp,
> +       .pingpong_count = ARRAY_SIZE(sm8650_pp),
> +       .pingpong = sm8650_pp,
> +       .dsc_count = ARRAY_SIZE(sm8650_dsc),
> +       .dsc = sm8650_dsc,
> +       .merge_3d_count = ARRAY_SIZE(sm8650_merge_3d),
> +       .merge_3d = sm8650_merge_3d,
> +       .wb_count = ARRAY_SIZE(sm8650_wb),
> +       .wb = sm8650_wb,
> +       .intf_count = ARRAY_SIZE(sm8650_intf),
> +       .intf = sm8650_intf,
> +       .vbif_count = ARRAY_SIZE(sm8650_vbif),
> +       .vbif = sm8650_vbif,
> +       .perf = &sm8650_perf_data,
> +};
> +
> +#endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index a1aada630780..0b8af44e12dd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -472,6 +472,7 @@ static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
>  static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
>  static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
>  static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
> +static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 6};

Just 7 of them?

>
>  static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
>         {
> @@ -558,6 +559,26 @@ static const struct dpu_vbif_cfg sm8550_vbif[] = {
>         },
>  };
>
> +static const struct dpu_vbif_cfg sm8650_vbif[] = {
> +       {
> +       .name = "vbif_rt", .id = VBIF_RT,
> +       .base = 0, .len = 0x1074,
> +       .features = BIT(DPU_VBIF_QOS_REMAP),
> +       .xin_halt_timeout = 0x4000,
> +       .qos_rp_remap_size = 0x40,
> +       .qos_rt_tbl = {
> +               .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),
> +               .priority_lvl = sm8650_rt_pri_lvl,
> +               },
> +       .qos_nrt_tbl = {
> +               .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
> +               .priority_lvl = sdm845_nrt_pri_lvl,
> +               },
> +       .memtype_count = 16,
> +       .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
> +       },
> +};
> +
>  /*************************************************************
>   * PERF data config
>   *************************************************************/
> @@ -673,3 +694,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>  #include "catalog/dpu_8_1_sm8450.h"
>
>  #include "catalog/dpu_9_0_sm8550.h"
> +
> +#include "catalog/dpu_10_0_sm8650.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index df024e10d3a3..92cce867a7e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -841,5 +841,6 @@ extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>  extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
>  extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
> +extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
>
>  #endif /* _DPU_HW_CATALOG_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index d85157acfbf8..a6702b2bfc68 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -195,6 +195,8 @@ enum dpu_pingpong {
>         PINGPONG_5,
>         PINGPONG_6,
>         PINGPONG_7,
> +       PINGPONG_8,
> +       PINGPONG_9,
>         PINGPONG_S0,
>         PINGPONG_MAX
>  };
> @@ -204,6 +206,7 @@ enum dpu_merge_3d {
>         MERGE_3D_1,
>         MERGE_3D_2,
>         MERGE_3D_3,
> +       MERGE_3D_4,
>         MERGE_3D_MAX
>  };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index fe7267b3bff5..4a017064207f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1363,6 +1363,7 @@ static const struct of_device_id dpu_dt_match[] = {
>         { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>         { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
>         { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
> +       { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
>         {}
>  };
>  MODULE_DEVICE_TABLE(of, dpu_dt_match);
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

Re: [PATCH 5/8] drm/msm: dpu1: add support for SM8650 DPU

[Neil Armstrong]

On 25/10/2023 09:49, Dmitry Baryshkov wrote:
> On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> Add DPU version 10.0 support for the SM8650 platform.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> 
> Thanks for your patch. Could you please rebase it on top of
> https://patchwork.freedesktop.org/series/119804/ ?

Sure, will do

Thanks,
Neil

> 
>> ---
>>   .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h    | 458 +++++++++++++++++++++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  23 ++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   3 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>>   5 files changed, 486 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
>> new file mode 100644
>> index 000000000000..3a37d78804e7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
>> @@ -0,0 +1,458 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DPU_10_0_SM8650_H
>> +#define _DPU_10_0_SM8650_H
>> +
>> +static const struct dpu_caps sm8650_dpu_caps = {
>> +       .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> +       .max_mixer_blendstages = 0xb,
>> +       .qseed_type = DPU_SSPP_SCALER_QSEED4,
>> +       .has_src_split = true,
>> +       .has_dim_layer = true,
>> +       .has_idle_pc = true,
>> +       .has_3d_merge = true,
>> +       .max_linewidth = 8192,
>> +       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>> +};
>> +
>> +static const struct dpu_mdp_cfg sm8650_mdp = {
>> +       .name = "top_0",
>> +       .base = 0, .len = 0x494,
>> +       .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
>> +       .clk_ctrls = {
>> +               [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
>> +       },
>> +};
>> +
>> +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
>> +static const struct dpu_ctl_cfg sm8650_ctl[] = {
>> +       {
>> +               .name = "ctl_0", .id = CTL_0,
>> +               .base = 0x15000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> +       }, {
>> +               .name = "ctl_1", .id = CTL_1,
>> +               .base = 0x16000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> +       }, {
>> +               .name = "ctl_2", .id = CTL_2,
>> +               .base = 0x17000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK,
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> +       }, {
>> +               .name = "ctl_3", .id = CTL_3,
>> +               .base = 0x18000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK,
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> +       }, {
>> +               .name = "ctl_4", .id = CTL_4,
>> +               .base = 0x19000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK,
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> +       }, {
>> +               .name = "ctl_5", .id = CTL_5,
>> +               .base = 0x1a000, .len = 0x1000,
>> +               .features = CTL_SM8550_MASK,
>> +               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> +       },
>> +};
>> +
>> +static const struct dpu_sspp_cfg sm8650_sspp[] = {
>> +       {
>> +               .name = "sspp_0", .id = SSPP_VIG0,
>> +               .base = 0x4000, .len = 0x344,
>> +               .features = VIG_SC7180_MASK,
> 
> Could you please use _SDMA mask here after testing that SmartDMA works
> as expected?
> 
>> +               .sblk = &sm8550_vig_sblk_0,
>> +               .xin_id = 0,
>> +               .type = SSPP_TYPE_VIG,
>> +       }, {
>> +               .name = "sspp_1", .id = SSPP_VIG1,
>> +               .base = 0x6000, .len = 0x344,
>> +               .features = VIG_SC7180_MASK,
>> +               .sblk = &sm8550_vig_sblk_1,
>> +               .xin_id = 4,
>> +               .type = SSPP_TYPE_VIG,
>> +       }, {
>> +               .name = "sspp_2", .id = SSPP_VIG2,
>> +               .base = 0x8000, .len = 0x344,
>> +               .features = VIG_SC7180_MASK,
>> +               .sblk = &sm8550_vig_sblk_2,
>> +               .xin_id = 8,
>> +               .type = SSPP_TYPE_VIG,
>> +       }, {
>> +               .name = "sspp_3", .id = SSPP_VIG3,
>> +               .base = 0xa000, .len = 0x344,
>> +               .features = VIG_SC7180_MASK,
>> +               .sblk = &sm8550_vig_sblk_3,
>> +               .xin_id = 12,
>> +               .type = SSPP_TYPE_VIG,
>> +       }, {
>> +               .name = "sspp_8", .id = SSPP_DMA0,
>> +               .base = 0x24000, .len = 0x344,
>> +               .features = DMA_SDM845_MASK,
>> +               .sblk = &sdm845_dma_sblk_0,
>> +               .xin_id = 1,
>> +               .type = SSPP_TYPE_DMA,
>> +       }, {
>> +               .name = "sspp_9", .id = SSPP_DMA1,
>> +               .base = 0x26000, .len = 0x344,
>> +               .features = DMA_SDM845_MASK,
>> +               .sblk = &sdm845_dma_sblk_1,
>> +               .xin_id = 5,
>> +               .type = SSPP_TYPE_DMA,
>> +       }, {
>> +               .name = "sspp_10", .id = SSPP_DMA2,
>> +               .base = 0x28000, .len = 0x344,
>> +               .features = DMA_SDM845_MASK,
>> +               .sblk = &sdm845_dma_sblk_2,
>> +               .xin_id = 9,
>> +               .type = SSPP_TYPE_DMA,
>> +       }, {
>> +               .name = "sspp_11", .id = SSPP_DMA3,
>> +               .base = 0x2a000, .len = 0x344,
>> +               .features = DMA_SDM845_MASK,
>> +               .sblk = &sdm845_dma_sblk_3,
>> +               .xin_id = 13,
>> +               .type = SSPP_TYPE_DMA,
>> +       }, {
>> +               .name = "sspp_12", .id = SSPP_DMA4,
>> +               .base = 0x2c000, .len = 0x344,
>> +               .features = DMA_CURSOR_SDM845_MASK,
>> +               .sblk = &sm8550_dma_sblk_4,
>> +               .xin_id = 14,
>> +               .type = SSPP_TYPE_DMA,
>> +       }, {
>> +               .name = "sspp_13", .id = SSPP_DMA5,
>> +               .base = 0x2e000, .len = 0x344,
>> +               .features = DMA_CURSOR_SDM845_MASK,
>> +               .sblk = &sm8550_dma_sblk_5,
>> +               .xin_id = 15,
>> +               .type = SSPP_TYPE_DMA,
>> +       },
>> +};
>> +
>> +static const struct dpu_lm_cfg sm8650_lm[] = {
>> +       {
>> +               .name = "lm_0", .id = LM_0,
>> +               .base = 0x44000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_1,
>> +               .pingpong = PINGPONG_0,
>> +               .dspp = DSPP_0,
>> +       }, {
>> +               .name = "lm_1", .id = LM_1,
>> +               .base = 0x45000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_0,
>> +               .pingpong = PINGPONG_1,
>> +               .dspp = DSPP_1,
>> +       }, {
>> +               .name = "lm_2", .id = LM_2,
>> +               .base = 0x46000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_3,
>> +               .pingpong = PINGPONG_2,
>> +       }, {
>> +               .name = "lm_3", .id = LM_3,
>> +               .base = 0x47000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_2,
>> +               .pingpong = PINGPONG_3,
>> +       }, {
>> +               .name = "lm_4", .id = LM_4,
>> +               .base = 0x48000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_5,
>> +               .pingpong = PINGPONG_4,
>> +       }, {
>> +               .name = "lm_5", .id = LM_5,
>> +               .base = 0x49000, .len = 0x400,
>> +               .features = MIXER_SDM845_MASK,
>> +               .sblk = &sdm845_lm_sblk,
>> +               .lm_pair = LM_4,
>> +               .pingpong = PINGPONG_5,
>> +       },
>> +};
>> +
>> +static const struct dpu_dspp_cfg sm8650_dspp[] = {
>> +       {
>> +               .name = "dspp_0", .id = DSPP_0,
>> +               .base = 0x54000, .len = 0x1800,
>> +               .features = DSPP_SC7180_MASK,
>> +               .sblk = &sdm845_dspp_sblk,
>> +       }, {
>> +               .name = "dspp_1", .id = DSPP_1,
>> +               .base = 0x56000, .len = 0x1800,
>> +               .features = DSPP_SC7180_MASK,
>> +               .sblk = &sdm845_dspp_sblk,
>> +       }, {
>> +               .name = "dspp_2", .id = DSPP_2,
>> +               .base = 0x58000, .len = 0x1800,
>> +               .features = DSPP_SC7180_MASK,
>> +               .sblk = &sdm845_dspp_sblk,
>> +       }, {
>> +               .name = "dspp_3", .id = DSPP_3,
>> +               .base = 0x5a000, .len = 0x1800,
>> +               .features = DSPP_SC7180_MASK,
>> +               .sblk = &sdm845_dspp_sblk,
>> +       },
>> +};
>> +
>> +static const struct dpu_pingpong_cfg sm8650_pp[] = {
>> +       {
>> +               .name = "pingpong_0", .id = PINGPONG_0,
>> +               .base = 0x69000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_0,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> +       }, {
>> +               .name = "pingpong_1", .id = PINGPONG_1,
>> +               .base = 0x6a000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_0,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> +       }, {
>> +               .name = "pingpong_2", .id = PINGPONG_2,
>> +               .base = 0x6b000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_1,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>> +       }, {
>> +               .name = "pingpong_3", .id = PINGPONG_3,
>> +               .base = 0x6c000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_1,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
>> +       }, {
>> +               .name = "pingpong_4", .id = PINGPONG_4,
>> +               .base = 0x6d000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_2,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
>> +       }, {
>> +               .name = "pingpong_5", .id = PINGPONG_5,
>> +               .base = 0x6e000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_2,
>> +               .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
>> +       }, {
>> +               .name = "pingpong_6", .id = PINGPONG_6,
>> +               .base = 0x66000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_3,
>> +       }, {
>> +               .name = "pingpong_7", .id = PINGPONG_7,
>> +               .base = 0x66400, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_3,
>> +       }, {
>> +               .name = "pingpong_8", .id = PINGPONG_8,
>> +               .base = 0x7e000, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_4,
>> +       }, {
>> +               .name = "pingpong_9", .id = PINGPONG_9,
>> +               .base = 0x7e400, .len = 0,
>> +               .features = BIT(DPU_PINGPONG_DITHER),
>> +               .sblk = &sc7280_pp_sblk,
>> +               .merge_3d = MERGE_3D_4,
>> +       },
>> +};
>> +
>> +static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = {
>> +       {
>> +               .name = "merge_3d_0", .id = MERGE_3D_0,
>> +               .base = 0x4e000, .len = 0x8,
>> +       }, {
>> +               .name = "merge_3d_1", .id = MERGE_3D_1,
>> +               .base = 0x4f000, .len = 0x8,
>> +       }, {
>> +               .name = "merge_3d_2", .id = MERGE_3D_2,
>> +               .base = 0x50000, .len = 0x8,
>> +       }, {
>> +               .name = "merge_3d_3", .id = MERGE_3D_3,
>> +               .base = 0x66700, .len = 0x8,
>> +       }, {
>> +               .name = "merge_3d_4", .id = MERGE_3D_4,
>> +               .base = 0x7e700, .len = 0x8,
>> +       },
>> +};
>> +
>> +/*
>> + * NOTE: Each display compression engine (DCE) contains dual hard
>> + * slice DSC encoders so both share same base address but with
>> + * its own different sub block address.
>> + */
>> +static const struct dpu_dsc_cfg sm8650_dsc[] = {
>> +       {
>> +               .name = "dce_0_0", .id = DSC_0,
>> +               .base = 0x80000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +               .sblk = &dsc_sblk_0,
>> +       }, {
>> +               .name = "dce_0_1", .id = DSC_1,
>> +               .base = 0x80000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +               .sblk = &dsc_sblk_1,
>> +       }, {
>> +               .name = "dce_1_0", .id = DSC_2,
>> +               .base = 0x81000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +               .sblk = &dsc_sblk_0,
>> +       }, {
>> +               .name = "dce_1_1", .id = DSC_3,
>> +               .base = 0x81000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
>> +               .sblk = &dsc_sblk_1,
>> +       }, {
>> +               .name = "dce_2_0", .id = DSC_4,
>> +               .base = 0x82000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2),
>> +               .sblk = &dsc_sblk_0,
>> +       }, {
>> +               .name = "dce_2_1", .id = DSC_5,
>> +               .base = 0x82000, .len = 0x6,
>> +               .features = BIT(DPU_DSC_HW_REV_1_2),
>> +               .sblk = &dsc_sblk_1,
>> +       },
>> +};
>> +
>> +static const struct dpu_wb_cfg sm8650_wb[] = {
>> +       {
>> +               .name = "wb_2", .id = WB_2,
>> +               .base = 0x65000, .len = 0x2c8,
>> +               .features = WB_SM8250_MASK,
>> +               .format_list = wb2_formats,
>> +               .num_formats = ARRAY_SIZE(wb2_formats),
>> +               .xin_id = 6,
>> +               .vbif_idx = VBIF_RT,
>> +               .maxlinewidth = 4096,
>> +               .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
>> +       },
>> +};
>> +
>> +static const struct dpu_intf_cfg sm8650_intf[] = {
>> +       {
>> +               .name = "intf_0", .id = INTF_0,
>> +               .base = 0x34000, .len = 0x280,
>> +               .features = INTF_SC7280_MASK,
>> +               .type = INTF_DP,
>> +               .controller_id = MSM_DP_CONTROLLER_0,
>> +               .prog_fetch_lines_worst_case = 24,
>> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
>> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
>> +       }, {
>> +               .name = "intf_1", .id = INTF_1,
>> +               .base = 0x35000, .len = 0x300,
>> +               .features = INTF_SC7280_MASK,
>> +               .type = INTF_DSI,
>> +               .controller_id = MSM_DSI_CONTROLLER_0,
>> +               .prog_fetch_lines_worst_case = 24,
>> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
>> +               .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
>> +       }, {
>> +               .name = "intf_2", .id = INTF_2,
>> +               .base = 0x36000, .len = 0x300,
>> +               .features = INTF_SC7280_MASK,
>> +               .type = INTF_DSI,
>> +               .controller_id = MSM_DSI_CONTROLLER_1,
>> +               .prog_fetch_lines_worst_case = 24,
>> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
>> +               .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
>> +       }, {
>> +               .name = "intf_3", .id = INTF_3,
>> +               .base = 0x37000, .len = 0x280,
>> +               .features = INTF_SC7280_MASK,
>> +               .type = INTF_DP,
>> +               .controller_id = MSM_DP_CONTROLLER_1,
>> +               .prog_fetch_lines_worst_case = 24,
>> +               .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>> +               .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
>> +       },
>> +};
>> +
>> +static const struct dpu_perf_cfg sm8650_perf_data = {
>> +       .max_bw_low = 17000000,
>> +       .max_bw_high = 27000000,
>> +       .min_core_ib = 2500000,
>> +       .min_llcc_ib = 0,
>> +       .min_dram_ib = 800000,
>> +       .min_prefill_lines = 35,
>> +       /* FIXME: lut tables */
>> +       .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
>> +       .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
>> +       .qos_lut_tbl = {
>> +               {.nentry = ARRAY_SIZE(sc7180_qos_linear),
>> +               .entries = sc7180_qos_linear
>> +               },
>> +               {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
>> +               .entries = sc7180_qos_macrotile
>> +               },
>> +               {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
>> +               .entries = sc7180_qos_nrt
>> +               },
>> +               /* TODO: macrotile-qseed is different from macrotile */
>> +       },
>> +       .cdp_cfg = {
>> +               {.rd_enable = 1, .wr_enable = 1},
>> +               {.rd_enable = 1, .wr_enable = 0}
>> +       },
>> +       .clk_inefficiency_factor = 105,
>> +       .bw_inefficiency_factor = 120,
>> +};
>> +
>> +static const struct dpu_mdss_version sm8650_mdss_ver = {
>> +       .core_major_ver = 10,
>> +       .core_minor_ver = 0,
>> +};
>> +
>> +const struct dpu_mdss_cfg dpu_sm8650_cfg = {
>> +       .mdss_ver = &sm8650_mdss_ver,
>> +       .caps = &sm8650_dpu_caps,
>> +       .mdp = &sm8650_mdp,
>> +       .ctl_count = ARRAY_SIZE(sm8650_ctl),
>> +       .ctl = sm8650_ctl,
>> +       .sspp_count = ARRAY_SIZE(sm8650_sspp),
>> +       .sspp = sm8650_sspp,
>> +       .mixer_count = ARRAY_SIZE(sm8650_lm),
>> +       .mixer = sm8650_lm,
>> +       .dspp_count = ARRAY_SIZE(sm8650_dspp),
>> +       .dspp = sm8650_dspp,
>> +       .pingpong_count = ARRAY_SIZE(sm8650_pp),
>> +       .pingpong = sm8650_pp,
>> +       .dsc_count = ARRAY_SIZE(sm8650_dsc),
>> +       .dsc = sm8650_dsc,
>> +       .merge_3d_count = ARRAY_SIZE(sm8650_merge_3d),
>> +       .merge_3d = sm8650_merge_3d,
>> +       .wb_count = ARRAY_SIZE(sm8650_wb),
>> +       .wb = sm8650_wb,
>> +       .intf_count = ARRAY_SIZE(sm8650_intf),
>> +       .intf = sm8650_intf,
>> +       .vbif_count = ARRAY_SIZE(sm8650_vbif),
>> +       .vbif = sm8650_vbif,
>> +       .perf = &sm8650_perf_data,
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index a1aada630780..0b8af44e12dd 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -472,6 +472,7 @@ static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
>>   static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
>>   static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
>>   static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
>> +static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 6};
> 
> Just 7 of them?
> 
>>
>>   static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
>>          {
>> @@ -558,6 +559,26 @@ static const struct dpu_vbif_cfg sm8550_vbif[] = {
>>          },
>>   };
>>
>> +static const struct dpu_vbif_cfg sm8650_vbif[] = {
>> +       {
>> +       .name = "vbif_rt", .id = VBIF_RT,
>> +       .base = 0, .len = 0x1074,
>> +       .features = BIT(DPU_VBIF_QOS_REMAP),
>> +       .xin_halt_timeout = 0x4000,
>> +       .qos_rp_remap_size = 0x40,
>> +       .qos_rt_tbl = {
>> +               .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),
>> +               .priority_lvl = sm8650_rt_pri_lvl,
>> +               },
>> +       .qos_nrt_tbl = {
>> +               .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
>> +               .priority_lvl = sdm845_nrt_pri_lvl,
>> +               },
>> +       .memtype_count = 16,
>> +       .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
>> +       },
>> +};
>> +
>>   /*************************************************************
>>    * PERF data config
>>    *************************************************************/
>> @@ -673,3 +694,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
>>   #include "catalog/dpu_8_1_sm8450.h"
>>
>>   #include "catalog/dpu_9_0_sm8550.h"
>> +
>> +#include "catalog/dpu_10_0_sm8650.h"
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index df024e10d3a3..92cce867a7e0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -841,5 +841,6 @@ extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
>>   extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
>> +extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
>>
>>   #endif /* _DPU_HW_CATALOG_H */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> index d85157acfbf8..a6702b2bfc68 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> @@ -195,6 +195,8 @@ enum dpu_pingpong {
>>          PINGPONG_5,
>>          PINGPONG_6,
>>          PINGPONG_7,
>> +       PINGPONG_8,
>> +       PINGPONG_9,
>>          PINGPONG_S0,
>>          PINGPONG_MAX
>>   };
>> @@ -204,6 +206,7 @@ enum dpu_merge_3d {
>>          MERGE_3D_1,
>>          MERGE_3D_2,
>>          MERGE_3D_3,
>> +       MERGE_3D_4,
>>          MERGE_3D_MAX
>>   };
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index fe7267b3bff5..4a017064207f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -1363,6 +1363,7 @@ static const struct of_device_id dpu_dt_match[] = {
>>          { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
>>          { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
>>          { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
>> +       { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
>>          {}
>>   };
>>   MODULE_DEVICE_TABLE(of, dpu_dt_match);
>>
>> --
>> 2.34.1
>>
> 
> 

[PATCH 6/8] drm/msm: mdss: add support for SM8650

[Neil Armstrong]

Add Mobile Display Subsystem (MDSS) support for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/msm_mdss.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 6865db1e3ce8..33947a2e313c 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -621,6 +621,7 @@ static const struct of_device_id mdss_dt_match[] = {
 	{ .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
 	{ .compatible = "qcom,sm8450-mdss", .data = &sm8250_data },
 	{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
+	{ .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
 	{}
 };
 MODULE_DEVICE_TABLE(of, mdss_dt_match);

-- 
2.34.1

Re: [PATCH 6/8] drm/msm: mdss: add support for SM8650

[Dmitry Baryshkov]

On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Add Mobile Display Subsystem (MDSS) support for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>  drivers/gpu/drm/msm/msm_mdss.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 6865db1e3ce8..33947a2e313c 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -621,6 +621,7 @@ static const struct of_device_id mdss_dt_match[] = {
>         { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data },
>         { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data },
>         { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
> +       { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
>         {}
>  };
>  MODULE_DEVICE_TABLE(of, mdss_dt_match);
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

[PATCH 7/8] drm/msm: dsi: add support for DSI-PHY on SM8650

[Neil Armstrong]

Add DSI PHY support for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c     |  2 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h     |  1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 05621e5e7d63..7612be6c3618 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
 	  .data = &dsi_phy_5nm_8450_cfgs },
 	{ .compatible = "qcom,sm8550-dsi-phy-4nm",
 	  .data = &dsi_phy_4nm_8550_cfgs },
+	{ .compatible = "qcom,sm8650-dsi-phy-4nm",
+	  .data = &dsi_phy_4nm_8650_cfgs },
 #endif
 	{}
 };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 8b640d174785..e4275d3ad581 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
 
 struct msm_dsi_dphy_timing {
 	u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d..c66193f2dc0d 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
 	{ .supply = "vdds", .init_load_uA = 37550 },
 };
 
+static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
+	{ .supply = "vdds", .init_load_uA = 98000 },
+};
+
 static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
 	{ .supply = "vdds", .init_load_uA = 97800 },
 };
@@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
 	.num_dsi_phy = 2,
 	.quirks = DSI_PHY_7NM_QUIRK_V5_2,
 };
+
+const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
+	.has_phy_lane = true,
+	.regulator_data = dsi_phy_7nm_98000uA_regulators,
+	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
+	.ops = {
+		.enable = dsi_7nm_phy_enable,
+		.disable = dsi_7nm_phy_disable,
+		.pll_init = dsi_pll_7nm_init,
+		.save_pll_state = dsi_7nm_pll_save_state,
+		.restore_pll_state = dsi_7nm_pll_restore_state,
+		.set_continuous_clock = dsi_7nm_set_continuous_clock,
+	},
+	.min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+	.max_pll_rate = 5000000000UL,
+#else
+	.max_pll_rate = ULONG_MAX,
+#endif
+	.io_start = { 0xae95000, 0xae97000 },
+	.num_dsi_phy = 2,
+	.quirks = DSI_PHY_7NM_QUIRK_V5_2,
+};

-- 
2.34.1

Re: [PATCH 7/8] drm/msm: dsi: add support for DSI-PHY on SM8650

[Dmitry Baryshkov]

On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Add DSI PHY support for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c     |  2 ++
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h     |  1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++
>  3 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 05621e5e7d63..7612be6c3618 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>           .data = &dsi_phy_5nm_8450_cfgs },
>         { .compatible = "qcom,sm8550-dsi-phy-4nm",
>           .data = &dsi_phy_4nm_8550_cfgs },
> +       { .compatible = "qcom,sm8650-dsi-phy-4nm",
> +         .data = &dsi_phy_4nm_8650_cfgs },
>  #endif
>         {}
>  };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 8b640d174785..e4275d3ad581 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
>
>  struct msm_dsi_dphy_timing {
>         u32 clk_zero;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 3b1ed02f644d..c66193f2dc0d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
>         { .supply = "vdds", .init_load_uA = 37550 },
>  };
>
> +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
> +       { .supply = "vdds", .init_load_uA = 98000 },
> +};
> +
>  static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
>         { .supply = "vdds", .init_load_uA = 97800 },
>  };
> @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
>         .num_dsi_phy = 2,
>         .quirks = DSI_PHY_7NM_QUIRK_V5_2,
>  };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {

So, this is the same as sm8550 config, just using 400 uA less? I
wonder if it makes sense to go for setting the regulator mode instead
of setting the load.

Nevertheless (unless you'd like to reuse sm8550 config entry):

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> +       .has_phy_lane = true,
> +       .regulator_data = dsi_phy_7nm_98000uA_regulators,
> +       .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
> +       .ops = {
> +               .enable = dsi_7nm_phy_enable,
> +               .disable = dsi_7nm_phy_disable,
> +               .pll_init = dsi_pll_7nm_init,
> +               .save_pll_state = dsi_7nm_pll_save_state,
> +               .restore_pll_state = dsi_7nm_pll_restore_state,
> +               .set_continuous_clock = dsi_7nm_set_continuous_clock,
> +       },
> +       .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> +       .max_pll_rate = 5000000000UL,
> +#else
> +       .max_pll_rate = ULONG_MAX,
> +#endif
> +       .io_start = { 0xae95000, 0xae97000 },
> +       .num_dsi_phy = 2,
> +       .quirks = DSI_PHY_7NM_QUIRK_V5_2,
> +};
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

Re: [PATCH 7/8] drm/msm: dsi: add support for DSI-PHY on SM8650

[Neil Armstrong]

On 25/10/2023 10:03, Dmitry Baryshkov wrote:
> On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> Add DSI PHY support for the SM8650 platform.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c     |  2 ++
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h     |  1 +
>>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++
>>   3 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> index 05621e5e7d63..7612be6c3618 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
>> @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>>            .data = &dsi_phy_5nm_8450_cfgs },
>>          { .compatible = "qcom,sm8550-dsi-phy-4nm",
>>            .data = &dsi_phy_4nm_8550_cfgs },
>> +       { .compatible = "qcom,sm8650-dsi-phy-4nm",
>> +         .data = &dsi_phy_4nm_8650_cfgs },
>>   #endif
>>          {}
>>   };
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> index 8b640d174785..e4275d3ad581 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
>> @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>>   extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
>> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
>>
>>   struct msm_dsi_dphy_timing {
>>          u32 clk_zero;
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 3b1ed02f644d..c66193f2dc0d 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
>>          { .supply = "vdds", .init_load_uA = 37550 },
>>   };
>>
>> +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
>> +       { .supply = "vdds", .init_load_uA = 98000 },
>> +};
>> +
>>   static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
>>          { .supply = "vdds", .init_load_uA = 97800 },
>>   };
>> @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
>>          .num_dsi_phy = 2,
>>          .quirks = DSI_PHY_7NM_QUIRK_V5_2,
>>   };
>> +
>> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
> 
> So, this is the same as sm8550 config, just using 400 uA less? I
> wonder if it makes sense to go for setting the regulator mode instead
> of setting the load.

I have no idea, we keep changing this but indeed we should instead change
the regulator mode, it's safer to keep it that way until we figure that out.

I'll double check anyway

> 
> Nevertheless (unless you'd like to reuse sm8550 config entry):
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Thanks,
Neil

> 
>> +       .has_phy_lane = true,
>> +       .regulator_data = dsi_phy_7nm_98000uA_regulators,
>> +       .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
>> +       .ops = {
>> +               .enable = dsi_7nm_phy_enable,
>> +               .disable = dsi_7nm_phy_disable,
>> +               .pll_init = dsi_pll_7nm_init,
>> +               .save_pll_state = dsi_7nm_pll_save_state,
>> +               .restore_pll_state = dsi_7nm_pll_restore_state,
>> +               .set_continuous_clock = dsi_7nm_set_continuous_clock,
>> +       },
>> +       .min_pll_rate = 600000000UL,
>> +#ifdef CONFIG_64BIT
>> +       .max_pll_rate = 5000000000UL,
>> +#else
>> +       .max_pll_rate = ULONG_MAX,
>> +#endif
>> +       .io_start = { 0xae95000, 0xae97000 },
>> +       .num_dsi_phy = 2,
>> +       .quirks = DSI_PHY_7NM_QUIRK_V5_2,
>> +};
>>
>> --
>> 2.34.1
>>
> 
> 

[PATCH 8/8] drm/msm: dsi: add support for DSI 2.8.0

[Neil Armstrong]

Add DSI Controller version 2.8.0 support for the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++
 drivers/gpu/drm/msm/dsi/dsi_cfg.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 1f98ff74ceb0..10ba7d153d1c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -190,6 +190,21 @@ static const struct msm_dsi_config sm8550_dsi_cfg = {
 	},
 };
 
+static const struct regulator_bulk_data sm8650_dsi_regulators[] = {
+	{ .supply = "vdda", .init_load_uA = 16600 },	/* 1.2 V */
+};
+
+static const struct msm_dsi_config sm8650_dsi_cfg = {
+	.io_offset = DSI_6G_REG_SHIFT,
+	.regulator_data = sm8650_dsi_regulators,
+	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
+	.bus_clk_names = dsi_v2_4_clk_names,
+	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
+	.io_start = {
+		{ 0xae94000, 0xae96000 },
+	},
+};
+
 static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
 	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
 	{ .supply = "refgen" },
@@ -281,6 +296,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
 		&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
 		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
+		&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
 };
 
 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 43f0dd74edb6..4c9b4b37681b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -28,6 +28,7 @@
 #define MSM_DSI_6G_VER_MINOR_V2_5_0	0x20050000
 #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000
 #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000
+#define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000
 
 #define MSM_DSI_V2_VER_MINOR_8064	0x0
 

-- 
2.34.1

Re: [PATCH 8/8] drm/msm: dsi: add support for DSI 2.8.0

[Dmitry Baryshkov]

On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Add DSI Controller version 2.8.0 support for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++
>  drivers/gpu/drm/msm/dsi/dsi_cfg.h |  1 +
>  2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> index 1f98ff74ceb0..10ba7d153d1c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
> @@ -190,6 +190,21 @@ static const struct msm_dsi_config sm8550_dsi_cfg = {
>         },
>  };
>
> +static const struct regulator_bulk_data sm8650_dsi_regulators[] = {
> +       { .supply = "vdda", .init_load_uA = 16600 },    /* 1.2 V */

Same comment regarding uA and sm8550 cfg.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> +};
> +
> +static const struct msm_dsi_config sm8650_dsi_cfg = {
> +       .io_offset = DSI_6G_REG_SHIFT,
> +       .regulator_data = sm8650_dsi_regulators,
> +       .num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
> +       .bus_clk_names = dsi_v2_4_clk_names,
> +       .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
> +       .io_start = {
> +               { 0xae94000, 0xae96000 },
> +       },
> +};
> +
>  static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
>         { .supply = "vdda", .init_load_uA = 8350 },     /* 1.2 V */
>         { .supply = "refgen" },
> @@ -281,6 +296,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
>                 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>         {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
>                 &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
> +       {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
> +               &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
>  };
>
>  const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> index 43f0dd74edb6..4c9b4b37681b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
> @@ -28,6 +28,7 @@
>  #define MSM_DSI_6G_VER_MINOR_V2_5_0    0x20050000
>  #define MSM_DSI_6G_VER_MINOR_V2_6_0    0x20060000
>  #define MSM_DSI_6G_VER_MINOR_V2_7_0    0x20070000
> +#define MSM_DSI_6G_VER_MINOR_V2_8_0    0x20080000
>
>  #define MSM_DSI_V2_VER_MINOR_8064      0x0
>
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry