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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id o20-20020ac25e34000000b004b40c2fccfdsm2226053lfg.59.2022.11.15.06.15.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Nov 2022 06:15:26 -0800 (PST) Message-ID: <2505fcf3-6c0c-b5f2-6400-bea9a1f7a70b@linaro.org> Date: Tue, 15 Nov 2022 15:15:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 4/9] dt-bindings: Add RISC-V incoming MSI controller bindings Content-Language: en-US To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20221111044207.1478350-1-apatel@ventanamicro.com> <20221111044207.1478350-5-apatel@ventanamicro.com> <9be58cb4-4ee8-a6e0-7a0a-f2f581e394d3@linaro.org> <3f469c79-fc4e-9c29-9c47-6dd8e28484a5@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 14/11/2022 16:04, Anup Patel wrote: > On Mon, Nov 14, 2022 at 5:52 PM Krzysztof Kozlowski >>>>> + riscv,slow-ipi: >>>>> + type: boolean >>>>> + description: >>>>> + The presence of this property implies that software interrupts (i.e. >>>>> + IPIs) using IMSIC software injected MSIs is slower compared to other >>>>> + software interrupt mechanisms (such as SBI IPI) on the underlying >>>>> + RISC-V platform. >>>> >>>> Is this a property of software or hardware? >>> >>> This is a property of hardware (or implementation) because IPIs >>> in IMSIC are software injected MSIs so if IMSIC is trap-n-emulated >>> by a hypervisor then all writes to MSI register will trap to hypervisor >>> in which case IPI injection via IMSIC is slow. >>> >>> The presence of "riscv,slow-ipi" DT property provides a hint to >>> driver that using IPIs through IMSIC is slow on this platform so >>> if there are other IPI mechanisms (such as SBI IPI calls) then >>> OS should prefer those mechanisms. >> >> If this is specific to implementation, why it is not included already in >> the compatible? >> >> The name is anyway too vague. What is "slow"? Describe real >> characteristics of hardware, e.g. trapped via hypervisor. > > Okay, how about renaming it to "riscv,trap-n-emulated" ? Sounds ok. > > Alternately, we can add "riscv,soft-imsics" as an implementation > specific compatible string which hypervisors can use to describe > trap-n-emulated IMSICs. This "riscv,soft-imsics" can also replace > "vendor,chip-imsics" dummy string ? soft-imsics would work only if it is a real device. My question was rather whether this is something configurable or fixed in given implementation. Best regards, Krzysztof