From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v3 3/5] PCI: st: Provide support for the sti PCIe controller Date: Sat, 11 Apr 2015 16:55:50 +0200 Message-ID: <2529595.kpEIoZMpcn@wuerfel> References: <1428657168-12495-1-git-send-email-gabriel.fernandez@linaro.org> <1428657168-12495-4-git-send-email-gabriel.fernandez@linaro.org> <1428747477.17822.90.camel@x220> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: In-Reply-To: <1428747477.17822.90.camel@x220> Sender: linux-pci-owner@vger.kernel.org To: Paul Bolle Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Viresh Kumar , Thierry List-Id: devicetree@vger.kernel.org On Saturday 11 April 2015 12:17:57 Paul Bolle wrote: > Something I didn't spot in my first look at this patch. > > On Fri, 2015-04-10 at 11:12 +0200, Gabriel FERNANDEZ wrote: > > --- a/drivers/pci/host/Kconfig > > +++ b/drivers/pci/host/Kconfig > > > > +config PCI_ST > > + bool "ST PCIe controller" > > + depends on ARCH_STI || (ARM && COMPILE_TEST) > > + select PCIE_DW > > + help > > + Enable PCIe controller support on ST Socs. This controller is based > > + on Designware hardware and therefore the driver re-uses the > > + Designware core functions to implement the driver. > > You can't have ARCH_STI without ARM, so ARM will always be set if this > driver is enabled. Correct? Right, though the ARM dependency could soon be dropped, once the PCIE_DW driver can use generic infrastructure in the few places it relies on ARM specific code today. > > --- /dev/null > > +++ b/drivers/pci/host/pci-st.c > > > + if (IS_ENABLED(CONFIG_ARM)) { > > + /* > > + * We have to hook the abort handler so that we can intercept > > + * bus errors when doing config read/write that return UR, > > + * which is flagged up as a bus error > > + */ > > + hook_fault_code(16+6, st_pcie_abort_handler, SIGBUS, 0, > > + "imprecise external abort"); > > + } > > So, unless I'm missing something obvious here, IS_ENABLED(CONFIG_ARM) > will always evaluate to 1. Can't that test be dropped? I would leave it in, as it's quite likely to get reused with ARM64 at some point in the future (no, I don't know anything about ST's product plans, but everybody seems to be doing this). Arnd