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[86.30.250.44]) by smtp.googlemail.com with ESMTPSA id 89sm7171745wrg.56.2020.06.17.08.19.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jun 2020 08:19:02 -0700 (PDT) Subject: Re: [PATCH v3 2/4] dt-bindings: nvmem: Add properties needed for blowing fuses To: Douglas Anderson , Rob Herring , Bjorn Andersson , Andy Gross Cc: dhavalp@codeaurora.org, mturney@codeaurora.org, rnayak@codeaurora.org, Ravi Kumar Bokka , linux-arm-msm@vger.kernel.org, saiprakash.ranjan@codeaurora.org, sparate@codeaurora.org, mkurumel@codeaurora.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20200617145116.247432-1-dianders@chromium.org> <20200617074930.v3.2.I3b5c3bfaf5fb2d28d63f1b5ee92980900e3f8251@changeid> From: Srinivas Kandagatla Message-ID: <254998b9-c45e-bd6b-bc9a-b5934c0fea8e@linaro.org> Date: Wed, 17 Jun 2020 16:19:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20200617074930.v3.2.I3b5c3bfaf5fb2d28d63f1b5ee92980900e3f8251@changeid> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/06/2020 15:51, Douglas Anderson wrote: > From: Ravi Kumar Bokka > > On some systems it's possible to actually blow the fuses in the qfprom > from the kernel. Add properties to support that. > > NOTE: Whether this is possible depends on the BIOS settings and > whether the kernel has permissions here, so not all boards will be > able to blow fuses in the kernel. > > Signed-off-by: Ravi Kumar Bokka > Signed-off-by: Douglas Anderson > --- > > Changes in v3: > - Add an extra reg range (at 0x6000 offset for SoCs checked) > - Define two options for reg: 1 item or 4 items. > - No reg-names. > - Add "clocks" and "clock-names" to list of properties. > - Clock is now "sec", not "secclk". > - Add "vcc-supply" to list of properties. > - Fixed up example. > > .../bindings/nvmem/qcom,qfprom.yaml | 45 ++++++++++++++++++- > 1 file changed, 43 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml > index 5efa5e7c4d81..b195212c6193 100644 > --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml > +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml > @@ -17,8 +17,27 @@ properties: > const: qcom,qfprom > > reg: > - items: > - - description: The corrected region. > + # If the QFPROM is read-only OS image then only the corrected region > + # needs to be provided. If the QFPROM is writable then all 4 regions > + # must be provided. > + oneOf: > + - items: > + - description: The corrected region. > + - items: > + - description: The corrected region. > + - description: The raw region. > + - description: The config region. > + - description: The security control region. > + > + # Clock must be provided if QFPROM is writable from the OS image. > + clocks: > + maxItems: 1 > + clock-names: > + const: sec Do we need clock-names for just one clock here? > + > + # Supply reference must be provided if QFPROM is writable from the OS image. > + vcc-supply: > + description: Our power supply. > > # Needed if any child nodes are present. > "#address-cells": > @@ -31,6 +50,28 @@ required: > - reg > > examples: > + - | > + #include > + > + efuse@784000 { > + compatible = "qcom,qfprom"; > + reg = <0 0x00784000 0 0x8ff>, > + <0 0x00780000 0 0x7a0>, > + <0 0x00782000 0 0x100>, > + <0 0x00786000 0 0x1fff>; > + clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; > + clock-names = "sec"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + vcc-supply = <&vreg_l11a_1p8>; > + > + hstx-trim-primary@25b { > + reg = <0x25b 0x1>; > + bits = <1 3>; > + }; > + }; > + > - | > efuse@784000 { > compatible = "qcom,qfprom"; >