From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references
Date: Fri, 07 Feb 2025 10:03:23 +0100 [thread overview]
Message-ID: <2568692.iZASKD2KPV@steina-w> (raw)
In-Reply-To: <20250207083616.1442887-11-alexander.stein@ew.tq-group.com>
Am Freitag, 7. Februar 2025, 09:36:15 CET schrieb Alexander Stein:
> Mark ocotp as a access-controller and add references on peripherals
> which can be disabled (fused).
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index df8ba1d5391ae..95a40cccd46b9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
I just noticed, I missed #access-controller-cells = <2>; for ocotp node.
Will add in next version.
Best regards,
Alexander
> @@ -12,6 +12,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
> #include <dt-bindings/interconnect/imx8mq.h>
> +#include "imx8mq-ocotp.h"
> #include "imx8mq-pinfunc.h"
>
> / {
> @@ -1275,6 +1276,7 @@ mipi_dsi: dsi@30a00000 {
> <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
> <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
> reset-names = "byte", "dpi", "esc", "pclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_DSI_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1392,6 +1394,7 @@ mipi_csi1: csi@30a70000 {
> fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
> interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
> interconnect-names = "dram";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1414,6 +1417,7 @@ csi1: csi@30a90000 {
> interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
> clock-names = "mclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI1_DISABLE>;
> status = "disabled";
>
> port {
> @@ -1444,6 +1448,7 @@ mipi_csi2: csi@30b60000 {
> fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
> interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
> interconnect-names = "dram";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
> status = "disabled";
>
> ports {
> @@ -1466,6 +1471,7 @@ csi2: csi@30b80000 {
> interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
> clock-names = "mclk";
> + access-controllers = <&ocotp IMX8MQ_OCOTP_MIPI_CSI2_DISABLE>;
> status = "disabled";
>
> port {
> @@ -1566,6 +1572,7 @@ fec1: ethernet@30be0000 {
> nvmem-cells = <&fec_mac_address>;
> nvmem-cell-names = "mac-address";
> fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_ENET_DISABLE>;
> status = "disabled";
> };
> };
> @@ -1705,6 +1712,7 @@ gpu: gpu@38000000 {
> <&clk IMX8MQ_GPU_PLL>;
> assigned-clock-rates = <800000000>, <800000000>,
> <800000000>, <800000000>, <0>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_GPU_DISABLE>;
> power-domains = <&pgc_gpu>;
> };
>
> @@ -1725,6 +1733,7 @@ usb_dwc3_0: usb@38100000 {
> phy-names = "usb2-phy", "usb3-phy";
> power-domains = <&pgc_otg1>;
> snps,parkmode-disable-ss-quirk;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG1_DISABLE>;
> status = "disabled";
> };
>
> @@ -1757,6 +1766,7 @@ usb_dwc3_1: usb@38200000 {
> phy-names = "usb2-phy", "usb3-phy";
> power-domains = <&pgc_otg2>;
> snps,parkmode-disable-ss-quirk;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_USB_OTG2_DISABLE>;
> status = "disabled";
> };
>
> @@ -1778,6 +1788,7 @@ vpu_g1: video-codec@38300000 {
> interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
> };
>
> vpu_g2: video-codec@38310000 {
> @@ -1786,6 +1797,7 @@ vpu_g2: video-codec@38310000 {
> interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_VPU_DISABLE>;
> };
>
> vpu_blk_ctrl: blk-ctrl@38320000 {
> @@ -1839,6 +1851,7 @@ pcie0: pcie@33800000 {
> <&clk IMX8MQ_SYS1_PLL_80M>;
> assigned-clock-rates = <250000000>, <100000000>,
> <10000000>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE1_DISABLE>;
> status = "disabled";
> };
>
> @@ -1882,6 +1895,7 @@ pcie1: pcie@33c00000 {
> <&clk IMX8MQ_SYS1_PLL_80M>;
> assigned-clock-rates = <250000000>, <100000000>,
> <10000000>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
> status = "disabled";
> };
>
> @@ -1916,6 +1930,7 @@ pcie1_ep: pcie-ep@33c00000 {
> <10000000>;
> num-ib-windows = <4>;
> num-ob-windows = <4>;
> + access-controllers = <&ocotp IMX8MQ_OCOTP_PCIE2_DISABLE>;
> status = "disabled";
> };
>
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
prev parent reply other threads:[~2025-02-07 9:05 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 8:36 [PATCH v2 00/10] Make i.MX8M OCOTP work as accessing controller Alexander Stein
2025-02-07 8:36 ` [PATCH v2 01/10] nvmem: imx-ocotp: Sort header alphabetically Alexander Stein
2025-02-07 8:36 ` [PATCH v2 02/10] nvmem: imx-ocotp: Support accessing controller for i.MX8M Alexander Stein
2025-02-07 15:22 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 03/10] arm64: dts: imx8mn: Add i.MX8M Nano OCOTP disable fuse definitions Alexander Stein
2025-02-07 11:54 ` Peng Fan
2025-02-07 8:36 ` [PATCH v2 04/10] arm64: dts: imx8mn: Add access-controller references Alexander Stein
2025-02-07 12:02 ` Peng Fan
2025-02-07 12:37 ` Alexander Stein
2025-02-10 2:36 ` Peng Fan
2025-02-10 15:48 ` Alexander Stein
2025-02-11 3:33 ` Peng Fan
2025-02-12 8:10 ` Alexander Stein
2025-02-12 8:22 ` Peng Fan
2025-02-07 8:36 ` [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions Alexander Stein
2025-02-07 15:23 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 06/10] arm64: dts: imx8mp: Add access-controller references Alexander Stein
2025-02-07 8:36 ` [PATCH v2 07/10] arm64: dts: imx8mm: Add i.MX8M Mini OCOTP disable fuse definitions Alexander Stein
2025-02-07 8:36 ` [PATCH v2 08/10] arm64: dts: imx8mm: Add access-controller references Alexander Stein
2025-02-07 8:36 ` [PATCH v2 09/10] arm64: dts: imx8mq: Add i.MX8M OCOTP disable fuse definitions Alexander Stein
2025-02-07 15:24 ` Frank Li
2025-02-07 8:36 ` [PATCH v2 10/10] arm64: dts: imx8mq: Add access-controller references Alexander Stein
2025-02-07 9:03 ` Alexander Stein [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2568692.iZASKD2KPV@steina-w \
--to=alexander.stein@ew.tq-group.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
--cc=srinivas.kandagatla@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).