From: Jie Luo <jie.luo@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: ipq5018: Enable MDIO buses and add ethernet PHY
Date: Thu, 20 Aug 2026 13:25:13 +0800 [thread overview]
Message-ID: <25c982a2-da65-4710-9412-e3cec66d2c3f@oss.qualcomm.com> (raw)
In-Reply-To: <ba2cd714-3da5-41ab-ae17-522d84f9d1c4@oss.qualcomm.com>
On 8/19/2026 8:42 PM, Konrad Dybcio wrote:
> On 8/14/26 4:22 PM, Luo Jie wrote:
>> Both the internal (mdio0) and external (mdio1) MDIO buses are present
>> in the SoC dtsi but left disabled at the board level, so the board
>> currently has no way to talk to PHYs on either bus.
>>
>> The RDP432-c2 board uses the SoC-integrated EPHY on mdio0 and an
>> external QCA8081 PHY on mdio1 for its Ethernet connections. Enable
>> mdio0 and mdio1 with a 6.25MHz MDIO clock, and describe the QCA8081
>> PHY at address 0x1c on mdio1.
>>
>> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> index 33eef92b19b1..aed8359b1931 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
>> @@ -30,6 +30,20 @@ &blsp1_uart1 {
>> status = "okay";
>> };
>>
>> +&mdio0 {
>> + clock-frequency = <6250000>;
>> + status = "okay";
>
> If the phy is integrated as part of the SoC, is there a reason to
> not enable this bus by default for all boards?
>
All IPQ5018 RDP boards use the integrated PHY and have this bus enabled.
I will move it to the SoC-level DTSI so that the bus is enabled by
default for all boards.
>> +};
>> +
>> +&mdio1 {
>> + clock-frequency = <6250000>;
>> + status = "okay";
>
> Nit: a newline before status would be neat
I will add the blank line before status in the next revision. Thanks.
>
>> +
>> + ethernet-phy@1c {
>
> No compatible string and other properties?
No compatible string is required here. This PHY QCA8081 supports both
Clause 22 and Clause 45 MDIO access, and its PHY ID can be read during
probe without any PHY-specific initialization. The standard PHY probing
flow is therefore sufficient with only the reg property.
>
> Konrad
prev parent reply other threads:[~2026-08-20 5:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-14 14:22 [PATCH v2 0/2] arm64: dts: qcom: ipq5018: Add MDIO pinctrl and enable MDIO/PHY on RDP432-c2 Luo Jie
2026-08-14 14:22 ` [PATCH v2 1/2] arm64: dts: qcom: ipq5018: Add pinctrl for MDIO bus Luo Jie
2026-08-19 12:40 ` Konrad Dybcio
2026-08-14 14:22 ` [PATCH v2 2/2] arm64: dts: qcom: ipq5018: Enable MDIO buses and add ethernet PHY Luo Jie
2026-08-19 12:42 ` Konrad Dybcio
2026-08-20 5:25 ` Jie Luo [this message]
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