From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 305772580F3; Wed, 22 Oct 2025 05:45:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761111956; cv=none; b=PP6a7NcviNgazQpqtl9yXHaJ5xMTkiJkEAGiSo1eeL76MpezgL+SS1Cao71XQuqJiYUAhoebwmWkTNGVUA35UqQDEEgHROOwBs91nzR4aVdB+0FL7bjOtLuZqBlRlwru/AplPuLzMfEIICyg+92erg1Gokkn9Gc1mTf5E0x2K0I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761111956; c=relaxed/simple; bh=X5q1//xUevpBMAGWrI/wonLI2iok8UTweOxWP6zvNFg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SOYQHRT96+XlZhJ7ocuJdLk/hY8UDUkbobNuV8r7vHyq1+QbuV+sUXYgkGtHQzrorf84alOe5AjM0p2xw03YDYgLpyQ4/u50Gfj8s17AC30pYTbWf6hDQWdDFv/Yryt+W6H+Pj6mC10RWbvIf9ecnuew9iIyO0A5dT88IiLx8iw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KEUXiDnW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KEUXiDnW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8EFB9C4CEE7; Wed, 22 Oct 2025 05:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761111955; bh=X5q1//xUevpBMAGWrI/wonLI2iok8UTweOxWP6zvNFg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KEUXiDnWtUZhor0zpSTi9a7ZAhT0eLtDZU4iUFzKOlOJ0nBC0wc63pJ8JMxtUXnmf HCSrL2r2cpnJ8QMFzvN19taR6kcC6j40etH+ZkksMpr7DQ+gd7NaqBnfTfS6HTab5p k58cyetwPYxiWrdOMsLnjMbHiHKJYx6HyFAuB6Bq9J8YmoaC/1elAK3XjtkoxzEpFL e3z4l1H0H6P+HJip2VDIpsbGQVTPRpb9W8h1cj0h1NnWi7GEpeM6MhwuTjMDsMaOEn R5eypHt9ZCn7gL4VsCh4w3IBDhf2J11IfV16g4s5zJaTn9e/GSQoi5MV5alnA+EPdF 4Dp1aCudO3Ghg== Message-ID: <25d6b64c-41b6-4431-870c-0b26d0cc4d03@kernel.org> Date: Wed, 22 Oct 2025 07:45:49 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/9] clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU To: Peter Griffin , Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Michael Turquette , Stephen Boyd , Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi , Will McVicker , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, kernel-team@android.com References: <20251013-automatic-clocks-v1-0-72851ee00300@linaro.org> <20251013-automatic-clocks-v1-8-72851ee00300@linaro.org> <4383c2fb-5267-4b7b-90e9-6046c2686912@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 21/10/2025 23:03, Peter Griffin wrote: >>> +} >>> + >>> static void __init gs101_cmu_misc_init(struct device_node *np) >>> { >>> + if (check_cmu_res_size(np)) >>> + return; >> >> You will not register CMU on old DTB. > > By "compatible" I meant the driver detects an old DTB with an > incorrect reg size and issues an error message on the console to > update your DT (as opposed to crashing trying to access a register > that hasn't been mapped). That's not being compatible. You should not break anything here if size is smaller - just fallback to previous manual mode. > > Is it enough to re-word the commit message to make it clearer what will happen? > > An alternative might be to try registering all the gates in manual > mode, but that seems like it would add more complexity for not much > benefit. It would also require that clk_ignore_unused kernel parameter > to have been passed (as manual clock mode has never worked without it) > and whilst it might boot today I imagine it would bitrot fast as > additional CMUs are added (and thus probably crash in a much more > obscure way). > > Peter Best regards, Krzysztof