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Thu, 12 Nov 2026 02:17:10 -0800 (PST) Received: from [10.218.21.154] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197d04336sm4026476a91.7.2026.11.12.02.17.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 02:17:10 -0800 (PST) Message-ID: <25ecc2ac-434f-4eea-b144-51fbc683201f@oss.qualcomm.com> Date: Thu, 12 Nov 2026 15:47:05 +0530 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 v6 4/9] ASoC: qcom: lpass-va-macro: Add shikra compatible To: Mark Brown Cc: Srinivas Kandagatla , Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261106-add_shikra_support-v6-0-2cda302237cc@oss.qualcomm.com> <20261106-add_shikra_support-v6-4-2cda302237cc@oss.qualcomm.com> <179436005594.790675.8837636459182556844.b4-review@b4> Content-Language: en-US From: Mohammad Rafi Shaik In-Reply-To: <179436005594.790675.8837636459182556844.b4-review@b4> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: AEzlAFD8tCZm23_HjOr9gkNt1x97_jLq X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEyMDA0MCBTYWx0ZWRfX08MR/JU83ZiT 8cPXlDUDf41Gkj6ebRsLy9G2NTXwQU4ysx0axcy58imLSbyzZKOf5o/ITRWrta+Ug9efSwS/UP7 kJfq9JrJhj6S8opiIuRH/+/4wudSxS4= X-Proofpoint-ORIG-GUID: AEzlAFD8tCZm23_HjOr9gkNt1x97_jLq X-Authority-Analysis: v=2.4 cv=d49gWhjE c=1 sm=1 tr=0 ts=6af59228 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=ea197RGUULTvqYrq9asA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEyMDA0MCBTYWx0ZWRfXz+OhYKderfv0 2q5X7C3k5dV0X/y9rVOMuC/sRbFk4Kmjz48r+06IysnKeKMgjpJPoWNyH09deCpUlT5cfu73TvX U3zJpOP2uCZXSBVEbLiSsWFh9Qt/IWPGjJwVPg6Ws7qAJ5m/zv3v7/X8FRD2jIFAIaZ5dQpJv62 tyvBP1K/z/NSABandwhxLomG/xpF+PufC75r8uYJz7UXrPaHZ7JwNMmV/P4/8PSOShyYfLvyrAj n3I6q6TlwMiZEjM2yx1xGkhYN9R9vtPjArDIWfgn9JIwCoLmahrZtbEHEWWbA6tq/kLd1tguGk8 1hXIaYPKx5xmW2Kt5vMnZj09a4XOou60sSHfMQZlvo5Q+9sZZSnW0jQAlUsM+vFK5FjoMQWyPE1 e6kjQ/zf2pDlQePVanfdatFehZjuxlXwcUJDxH1G9NQ8ORkl/ys7DB3rnuBUDBtyIb6Gc2gS9pz Ufp9hNnQbf9WhXlP0QQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-12_01,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611120040 On 11/11/2026 6:50 AM, Mark Brown wrote: >> Add shikra specific VA macro data and register programming needed by >> the LPASS codec v4.1 implementation. > >> +/* LPASS codec v4.1 adaptive filter (ADPT) blocks */ >> +#define CDC_VA_CDC_ADPT0_ADPT_CTRL 0x0800 >> +#define CDC_VA_ADPT_CTRL_EN_MASK GENMASK(7, 0) > > Is the enable mask really 8 bits wide? > Good catch Mark, it's actually 6 bits. will current in next version. >> +static const struct reg_default va_4_1_defaults[] = { >> + /* VA macro */ >> + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, >> + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, >> + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, >> + { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, >> + { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, >> + { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, >> + { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, >> + { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, >> + { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, >> + { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, >> + { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, >> + { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, >> + { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, >> + { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, >> + { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, >> + { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, >> + { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, >> + { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, >> + { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, >> + { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, >> + { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, >> + { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, >> + /* VA core */ >> + { CDC_VA_TX0_TX_PATH_CTL, 0x04}, > > Are we missing defaults for the mux registers? I missed in this version. will fix in next revision Best Regards, Rafi. >