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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id l28-20020ac24a9c000000b004b50b4f63b7sm2593666lfp.170.2022.12.28.02.30.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Dec 2022 02:30:16 -0800 (PST) Message-ID: <262fb9c4-c7d3-989f-c3fb-3e36da26b081@linaro.org> Date: Wed, 28 Dec 2022 11:30:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221227013225.2847382-1-dmitry.baryshkov@linaro.org> <20221227013225.2847382-2-dmitry.baryshkov@linaro.org> Content-Language: en-US From: Krzysztof Kozlowski In-Reply-To: <20221227013225.2847382-2-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27/12/2022 02:32, Dmitry Baryshkov wrote: > Define clock/clock-names properties of the GCC device node to be used > on APQ8084 platform. > > Note: the driver uses a single pcie_pipe clock, however most probably > there are two pipe clocks, one from each of PCIe QMP PHYs. > > Signed-off-by: Dmitry Baryshkov > --- > .../bindings/clock/qcom,gcc-apq8084.yaml | 43 +++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > index 8ade176c24f4..02a856f14fbe 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml > @@ -25,6 +25,30 @@ properties: > compatible: > const: qcom,gcc-apq8084 > > + clocks: > + items: > + - description: XO source > + - description: Sleep clock source > + - description: UFS RX symbol 0 clock > + - description: UFS RX symbol 1 clock > + - description: UFS TX symbol 0 clock > + - description: UFS TX symbol 1 clock > + - description: SATA ASIC0 clock > + - description: SATA RX clock > + - description: PCIe PIPE clock > + > + clock-names: > + items: > + - const: xo > + - const: sleep_clk > + - const: ufs_rx_symbol_0_clk_src > + - const: ufs_rx_symbol_1_clk_src > + - const: ufs_tx_symbol_0_clk_src > + - const: ufs_tx_symbol_1_clk_src > + - const: sata_asic0_clk > + - const: sata_rx_clk > + - const: pcie_pipe > + > required: > - compatible > > @@ -38,5 +62,24 @@ examples: > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > + > + clocks = <&xo_board>, > + <&sleep_clk>, > + <&ufsphy 0>, No IDs available yet? Best regards, Krzysztof