[RFC PATCHv2 2/9] dt-bindings: display/ti: add k2g-dss bindings

[RFC PATCHv2 2/9] dt-bindings: display/ti: add k2g-dss bindings

[Tomi Valkeinen]

Add DT bindings for Texas Instruments K2G SoC Display Subsystem. The DSS
is quite simple, with a single plane and a single output.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/display/ti/ti,k2g-dss.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt

diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
new file mode 100644
index 000000000000..1af11425eda3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
@@ -0,0 +1,15 @@
+Texas Instruments K2G Display Subsystem
+=======================================
+
+Required properties:
+- compatible: "ti,k2g-dss"
+- reg: address and length of the register spaces for DSS submodules
+- reg-names: "cfg", "common", "vid1", "ovr1", "vp1"
+- clocks: phandle to fclk and vp1 clocks
+- clock-names: "fck", "vp1"
+- interrupts: phandle to the DISPC interrupt
+
+The DSS outputs are described using the device graphs as documented in
+Documentation/devicetree/bindings/graph.txt. K2G DSS has a single DPI output as
+port 0.
+
-- 
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Re: [RFC PATCHv2 2/9] dt-bindings: display/ti: add k2g-dss bindings

[Laurent Pinchart]

Hi Tomi,

Thank you for the patch.

On Monday, 18 June 2018 16:22:35 EEST Tomi Valkeinen wrote:
> Add DT bindings for Texas Instruments K2G SoC Display Subsystem. The DSS
> is quite simple, with a single plane and a single output.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: devicetree@vger.kernel.org
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/display/ti/ti,k2g-dss.txt | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
> b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt new file mode
> 100644
> index 000000000000..1af11425eda3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
> @@ -0,0 +1,15 @@
> +Texas Instruments K2G Display Subsystem
> +=======================================
> +
> +Required properties:
> +- compatible: "ti,k2g-dss"
> +- reg: address and length of the register spaces for DSS submodules
> +- reg-names: "cfg", "common", "vid1", "ovr1", "vp1"

When seeing multiple register ranges for a DT node I always suspect that we 
describe multiple IP cores that could be better modeled as independent nodes. 
What prompted you not to model the DISPC as a separate DT node (possibly a 
child of the DSS DT node) ?

Furthermore, "cfg" corresponds to the DSS registers, so I wonder whether it 
shouldn't be named "dss". Similarly, "common" really sounds like DSS common 
registers, while it relates to the DISPC.

> +- clocks: phandle to fclk and vp1 clocks
> +- clock-names: "fck", "vp1"
> +- interrupts: phandle to the DISPC interrupt
> +
> +The DSS outputs are described using the device graphs as documented in
> +Documentation/devicetree/bindings/graph.txt. K2G DSS has a single DPI
> output as
> +port 0.

Both SPRUHY8H and SPRSP07D document a DPI output and a DBI output. Am I 
looking at the wrong document ?

> +

Extra blank line ?

-- 
Regards,

Laurent Pinchart



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Re: [RFC PATCHv2 2/9] dt-bindings: display/ti: add k2g-dss bindings

[Tomi Valkeinen]

On 24/07/18 17:29, Laurent Pinchart wrote:
> Hi Tomi,
> 
> Thank you for the patch.
> 
> On Monday, 18 June 2018 16:22:35 EEST Tomi Valkeinen wrote:
>> Add DT bindings for Texas Instruments K2G SoC Display Subsystem. The DSS
>> is quite simple, with a single plane and a single output.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: devicetree@vger.kernel.org
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>  .../devicetree/bindings/display/ti/ti,k2g-dss.txt | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>  create mode 100644
>> Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
>> b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt new file mode
>> 100644
>> index 000000000000..1af11425eda3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.txt
>> @@ -0,0 +1,15 @@
>> +Texas Instruments K2G Display Subsystem
>> +=======================================
>> +
>> +Required properties:
>> +- compatible: "ti,k2g-dss"
>> +- reg: address and length of the register spaces for DSS submodules
>> +- reg-names: "cfg", "common", "vid1", "ovr1", "vp1"
> 
> When seeing multiple register ranges for a DT node I always suspect that we 
> describe multiple IP cores that could be better modeled as independent nodes. 
> What prompted you not to model the DISPC as a separate DT node (possibly a 
> child of the DSS DT node) ?

Yes, it's been difficult to figure out the IP boundaries at times. Well,
the vid, ovr and vp regions are part of the DISPC IP, that's clear. The
question is with DSS (core) and DISPC.

On K2G, DSS and DISPC are indeed separate IPs, similar to OMAPs. DSS
("cfg" region here) is just a wrapper and has only a few registers, though.

On AM6, that's not the case, and there's only a single IP.

The reason to represent K2G DSS as a single DT node is just
practicality: there's no benefit that I can see to consider DSS and
DISPC as separate IPs, but it does cause problems in the SW side,
especially now that we want to support AM6 DSS too, which does not have
separate DSS and DISPC IPs.

The main problem there was the question about DRM device: is it the DSS
or the DISPC? From DRM point of view, the only sane answer is that DISPC
is the DRM device, as that's really the display IP and has the
interrupts etc. That then leaves the DSS device kind of hanging around.

Considering DSS and DISCP as a single device removed all the problems I
had. I think omapdrm driver would also be much simpler with this approach.

> Furthermore, "cfg" corresponds to the DSS registers, so I wonder whether it 
> shouldn't be named "dss". Similarly, "common" really sounds like DSS common 
> registers, while it relates to the DISPC.

"cfg" corresponds to the DSSUL_0_CFG in the TRM and "common" to the
DISPC_COMMON region. If you consider there to be only one DSS/DISPC IP,
then the naming makes more sense, as "cfg" is about the main level
config, "common" is about common stuff (to all planes and videoports).

>> +- clocks: phandle to fclk and vp1 clocks
>> +- clock-names: "fck", "vp1"
>> +- interrupts: phandle to the DISPC interrupt
>> +
>> +The DSS outputs are described using the device graphs as documented in
>> +Documentation/devicetree/bindings/graph.txt. K2G DSS has a single DPI
>> output as
>> +port 0.
> 
> Both SPRUHY8H and SPRSP07D document a DPI output and a DBI output. Am I 
> looking at the wrong document ?

No, you're right, it has DBI. I'm quite sure it was descoped at some
point, though, but it seems to be there in the final ones. We don't
support DBI in the driver, so we've missed it.

So I'll add the node to the DT.

 Tomi

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[RFC PATCHv2 3/9] dt-bindings: display/ti: add am65x-dss bindings

[Tomi Valkeinen]

Add DT bindings for Texas Instruments AM65x SoC Display Subsystem.  The
DSS7 on AM65x SoC has two video ports (DPI and OLDI) and two video
pipelines.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
---
 .../bindings/display/ti/ti,am6-dss.txt           | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt

diff --git a/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
new file mode 100644
index 000000000000..3466f095fb84
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
@@ -0,0 +1,16 @@
+Texas Instruments AM65x Display Subsystem
+==========================================
+
+Required properties:
+- compatible: "ti,am65x-dss", "ti,am6-dss"
+- reg: address and length of the register spaces for DSS submodules
+- reg-names: "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"
+- clocks: phandle to fclk, vp1, and vp2 clocks
+- clock-names: "fck", "vp1", "vp2"
+- interrupts: phandle to the DISPC interrupt
+- syscon: phandle to syscon device handling OLDI_PWRDN_TX (partition 1 of
+  AM654 CTRL MMR0)
+
+The DSS outputs are described using the device graphs as documented in
+Documentation/devicetree/bindings/graph.txt. AM6 DSS has a DPI output as port 0
+and an OLDI output as port 1.
-- 
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Re: [RFC PATCHv2 3/9] dt-bindings: display/ti: add am65x-dss bindings

[Rob Herring]

On Mon, Jun 18, 2018 at 04:22:36PM +0300, Tomi Valkeinen wrote:
> Add DT bindings for Texas Instruments AM65x SoC Display Subsystem.  The
> DSS7 on AM65x SoC has two video ports (DPI and OLDI) and two video
> pipelines.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: devicetree@vger.kernel.org
> ---
>  .../bindings/display/ti/ti,am6-dss.txt           | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> new file mode 100644
> index 000000000000..3466f095fb84
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> @@ -0,0 +1,16 @@
> +Texas Instruments AM65x Display Subsystem
> +==========================================
> +
> +Required properties:
> +- compatible: "ti,am65x-dss", "ti,am6-dss"

Why do you need 2 compatibles? What's the difference for the 'x' in 
'am65x'?

> +- reg: address and length of the register spaces for DSS submodules
> +- reg-names: "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"
> +- clocks: phandle to fclk, vp1, and vp2 clocks
> +- clock-names: "fck", "vp1", "vp2"

fck or fclk?

> +- interrupts: phandle to the DISPC interrupt
> +- syscon: phandle to syscon device handling OLDI_PWRDN_TX (partition 1 of
> +  AM654 CTRL MMR0)
> +
> +The DSS outputs are described using the device graphs as documented in
> +Documentation/devicetree/bindings/graph.txt. AM6 DSS has a DPI output as port 0
> +and an OLDI output as port 1.

What's OLDI?

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Re: [RFC PATCHv2 3/9] dt-bindings: display/ti: add am65x-dss bindings

[Tomi Valkeinen]

Hi Rob,

On 25/06/18 21:59, Rob Herring wrote:
> On Mon, Jun 18, 2018 at 04:22:36PM +0300, Tomi Valkeinen wrote:
>> Add DT bindings for Texas Instruments AM65x SoC Display Subsystem.  The
>> DSS7 on AM65x SoC has two video ports (DPI and OLDI) and two video
>> pipelines.
>>
>> Signed-off-by: Jyri Sarha <jsarha@ti.com>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: devicetree@vger.kernel.org
>> ---
>>  .../bindings/display/ti/ti,am6-dss.txt           | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>> new file mode 100644
>> index 000000000000..3466f095fb84
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>> @@ -0,0 +1,16 @@
>> +Texas Instruments AM65x Display Subsystem
>> +==========================================
>> +
>> +Required properties:
>> +- compatible: "ti,am65x-dss", "ti,am6-dss"
> 
> Why do you need 2 compatibles? What's the difference for the 'x' in 
> 'am65x'?

For now we have only one AM6xx SoC, but probably there will be more
variants, possibly with slightly different DSS setups (say, a single
output version). But then, maybe all the variants will have the exact
same DSS.

I'm not quite sure how to handle it here, so I added am6-dss as a base,
so that in the DT file we could have the compatible as
"exact-model-name","am6-dss", and only handle am6-dss in the driver
unless we get models with different DSS features.

But then I probably should not use am65x, and instead use the exact
model name here (am654), even if the last number in the model should not
affect DSS.

>> +- reg: address and length of the register spaces for DSS submodules
>> +- reg-names: "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"
>> +- clocks: phandle to fclk, vp1, and vp2 clocks
>> +- clock-names: "fck", "vp1", "vp2"
> 
> fck or fclk?

fck. I'll fix that.

>> +- interrupts: phandle to the DISPC interrupt
>> +- syscon: phandle to syscon device handling OLDI_PWRDN_TX (partition 1 of
>> +  AM654 CTRL MMR0)
>> +
>> +The DSS outputs are described using the device graphs as documented in
>> +Documentation/devicetree/bindings/graph.txt. AM6 DSS has a DPI output as port 0
>> +and an OLDI output as port 1.
> 
> What's OLDI?

OpenLDI (https://en.wikipedia.org/wiki/OpenLDI). I should probably not
abbreviate it here.

 Tomi


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Re: [RFC PATCHv2 3/9] dt-bindings: display/ti: add am65x-dss bindings

[Laurent Pinchart]

Hi Tomi,

Thank you for the patch.

On Monday, 18 June 2018 16:22:36 EEST Tomi Valkeinen wrote:
> Add DT bindings for Texas Instruments AM65x SoC Display Subsystem.  The
> DSS7 on AM65x SoC has two video ports (DPI and OLDI) and two video
> pipelines.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: devicetree@vger.kernel.org
> ---
>  .../bindings/display/ti/ti,am6-dss.txt           | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt new file mode
> 100644
> index 000000000000..3466f095fb84
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
> @@ -0,0 +1,16 @@
> +Texas Instruments AM65x Display Subsystem
> +==========================================
> +
> +Required properties:
> +- compatible: "ti,am65x-dss", "ti,am6-dss"
> +- reg: address and length of the register spaces for DSS submodules
> +- reg-names: "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"
> +- clocks: phandle to fclk, vp1, and vp2 clocks
> +- clock-names: "fck", "vp1", "vp2"
> +- interrupts: phandle to the DISPC interrupt
> +- syscon: phandle to syscon device handling OLDI_PWRDN_TX (partition 1 of
> +  AM654 CTRL MMR0)
> +
> +The DSS outputs are described using the device graphs as documented in
> +Documentation/devicetree/bindings/graph.txt. AM6 DSS has a DPI output as
> port 0
> +and an OLDI output as port 1.

Without documentation for the AM65x it's hard to review these DT bindings. 
However, my comment regarding the registers of the k2g-dss bindings applies 
here too.

-- 
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Laurent Pinchart



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Re: [RFC PATCHv2 3/9] dt-bindings: display/ti: add am65x-dss bindings

[Tomi Valkeinen]

On 30/07/18 02:04, Laurent Pinchart wrote:
> Hi Tomi,
> 
> Thank you for the patch.
> 
> On Monday, 18 June 2018 16:22:36 EEST Tomi Valkeinen wrote:
>> Add DT bindings for Texas Instruments AM65x SoC Display Subsystem.  The
>> DSS7 on AM65x SoC has two video ports (DPI and OLDI) and two video
>> pipelines.
>>
>> Signed-off-by: Jyri Sarha <jsarha@ti.com>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: devicetree@vger.kernel.org
>> ---
>>  .../bindings/display/ti/ti,am6-dss.txt           | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>  create mode 100644
>> Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>> b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt new file mode
>> 100644
>> index 000000000000..3466f095fb84
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am6-dss.txt
>> @@ -0,0 +1,16 @@
>> +Texas Instruments AM65x Display Subsystem
>> +==========================================
>> +
>> +Required properties:
>> +- compatible: "ti,am65x-dss", "ti,am6-dss"
>> +- reg: address and length of the register spaces for DSS submodules
>> +- reg-names: "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"
>> +- clocks: phandle to fclk, vp1, and vp2 clocks
>> +- clock-names: "fck", "vp1", "vp2"
>> +- interrupts: phandle to the DISPC interrupt
>> +- syscon: phandle to syscon device handling OLDI_PWRDN_TX (partition 1 of
>> +  AM654 CTRL MMR0)
>> +
>> +The DSS outputs are described using the device graphs as documented in
>> +Documentation/devicetree/bindings/graph.txt. AM6 DSS has a DPI output as
>> port 0
>> +and an OLDI output as port 1.
> 
> Without documentation for the AM65x it's hard to review these DT bindings. 
> However, my comment regarding the registers of the k2g-dss bindings applies 
> here too.

Sorry that I didn't provide the link. I guess it's not easily found from
ti.com at the moment:

http://www.ti.com/lit/ug/spruid7/spruid7.pdf

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[RFC PATCHv2 8/9] ARM: dts: keystone-k2g: add DSS node

[Tomi Valkeinen]

Add DSS node to k2g.dtsi.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
---
 arch/arm/boot/dts/keystone-k2g.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index da78c0034427..d761fe7d46e7 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -609,5 +609,26 @@
 			reg = <0x21010000 0x200>;
 			interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
 		};
+
+		dss: dss@02540000 {
+			compatible = "ti,k2g-dss";
+
+			reg = <0x02540000 0x400>,
+			      <0x02550000 0x1000>,
+			      <0x02557000 0x1000>,
+			      <0x0255a800 0x100>,
+			      <0x0255ac00 0x100>;
+
+			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
+
+			clocks = <&k2g_clks 0x2 0>, <&k2g_clks 0x2 1>;
+			clock-names = "fck", "vp1";
+
+			power-domains = <&k2g_pds 0x2>;
+
+			interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
+
+			status = "disabled";
+		};
 	};
 };
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Re: [RFC PATCHv2 8/9] ARM: dts: keystone-k2g: add DSS node

[Tony Lindgren]

* Tomi Valkeinen <tomi.valkeinen@ti.com> [180618 13:26]:
> Add DSS node to k2g.dtsi.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: devicetree@vger.kernel.org
> ---
>  arch/arm/boot/dts/keystone-k2g.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
> index da78c0034427..d761fe7d46e7 100644
> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> @@ -609,5 +609,26 @@
>  			reg = <0x21010000 0x200>;
>  			interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
>  		};
> +
> +		dss: dss@02540000 {
> +			compatible = "ti,k2g-dss";
> +
> +			reg = <0x02540000 0x400>,
> +			      <0x02550000 0x1000>,
> +			      <0x02557000 0x1000>,
> +			      <0x0255a800 0x100>,
> +			      <0x0255ac00 0x100>;
> +
> +			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";

Can you please check to make sure these are not multiple
separate devices?

If they are, flushing posted write to one device will not flush
anything to the other devices. And that can lead to very hard
to track down mysterious bugs.

Regards,

Tony
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Re: [RFC PATCHv2 8/9] ARM: dts: keystone-k2g: add DSS node

[Tomi Valkeinen]

On 19/06/18 09:19, Tony Lindgren wrote:
> * Tomi Valkeinen <tomi.valkeinen@ti.com> [180618 13:26]:
>> Add DSS node to k2g.dtsi.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
>> Cc: devicetree@vger.kernel.org
>> ---
>>  arch/arm/boot/dts/keystone-k2g.dtsi | 21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
>> index da78c0034427..d761fe7d46e7 100644
>> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
>> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
>> @@ -609,5 +609,26 @@
>>  			reg = <0x21010000 0x200>;
>>  			interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
>>  		};
>> +
>> +		dss: dss@02540000 {
>> +			compatible = "ti,k2g-dss";
>> +
>> +			reg = <0x02540000 0x400>,
>> +			      <0x02550000 0x1000>,
>> +			      <0x02557000 0x1000>,
>> +			      <0x0255a800 0x100>,
>> +			      <0x0255ac00 0x100>;
>> +
>> +			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
> 
> Can you please check to make sure these are not multiple
> separate devices?
> 
> If they are, flushing posted write to one device will not flush
> anything to the other devices. And that can lead to very hard
> to track down mysterious bugs.

I don't see anything hinting that they would be separate devices, and it
wouldn't really make sense to me either. They're integral parts of the
DISPC. I can see a single port for register access, and a single port
for the pixel data DMA.

 Tomi

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Re: [RFC PATCHv2 8/9] ARM: dts: keystone-k2g: add DSS node

[Tony Lindgren]

* Tomi Valkeinen <tomi.valkeinen@ti.com> [180619 07:12]:
> On 19/06/18 09:19, Tony Lindgren wrote:
> > * Tomi Valkeinen <tomi.valkeinen@ti.com> [180618 13:26]:
> >> Add DSS node to k2g.dtsi.
> >>
> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >> Cc: devicetree@vger.kernel.org
> >> ---
> >>  arch/arm/boot/dts/keystone-k2g.dtsi | 21 +++++++++++++++++++++
> >>  1 file changed, 21 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
> >> index da78c0034427..d761fe7d46e7 100644
> >> --- a/arch/arm/boot/dts/keystone-k2g.dtsi
> >> +++ b/arch/arm/boot/dts/keystone-k2g.dtsi
> >> @@ -609,5 +609,26 @@
> >>  			reg = <0x21010000 0x200>;
> >>  			interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
> >>  		};
> >> +
> >> +		dss: dss@02540000 {
> >> +			compatible = "ti,k2g-dss";
> >> +
> >> +			reg = <0x02540000 0x400>,
> >> +			      <0x02550000 0x1000>,
> >> +			      <0x02557000 0x1000>,
> >> +			      <0x0255a800 0x100>,
> >> +			      <0x0255ac00 0x100>;
> >> +
> >> +			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
> > 
> > Can you please check to make sure these are not multiple
> > separate devices?
> > 
> > If they are, flushing posted write to one device will not flush
> > anything to the other devices. And that can lead to very hard
> > to track down mysterious bugs.
> 
> I don't see anything hinting that they would be separate devices, and it
> wouldn't really make sense to me either. They're integral parts of the
> DISPC. I can see a single port for register access, and a single port
> for the pixel data DMA.

OK thanks for checking.

Tony
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[RFC PATCHv2 9/9] ARM: dts: keystone-k2g-evm: add LCD and HDMI displays

[Tomi Valkeinen]

K2G EVM has an SiI902x HDMI encoder on the board, and a separately
purchasable LCD which can be attached to the board. Only one of these
displays can be used at a time, and two dip-switches need to be changed
when switching to another display.

The HDMI support is added to the base k2g-evm.dts file, and the LCD
support is added as a separate k2g-evm-lcd.dts file. The user must
choose one of the dtbs, depending on which display he wants to use.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
---
 arch/arm/boot/dts/Makefile                 |  1 +
 arch/arm/boot/dts/keystone-k2g-evm-lcd.dts | 80 ++++++++++++++++++++
 arch/arm/boot/dts/keystone-k2g-evm.dts     | 87 ++++++++++++++++++++++
 3 files changed, 168 insertions(+)
 create mode 100644 arch/arm/boot/dts/keystone-k2g-evm-lcd.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e2424957809..11bb3ba22bdf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -222,6 +222,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \
 	keystone-k2l-evm.dtb \
 	keystone-k2e-evm.dtb \
 	keystone-k2g-evm.dtb \
+	keystone-k2g-evm-lcd.dtb \
 	keystone-k2g-ice.dtb
 dtb-$(CONFIG_MACH_KIRKWOOD) += \
 	kirkwood-b3.dtb \
diff --git a/arch/arm/boot/dts/keystone-k2g-evm-lcd.dts b/arch/arm/boot/dts/keystone-k2g-evm-lcd.dts
new file mode 100644
index 000000000000..be0498010e71
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-k2g-evm-lcd.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for K2G EVM with LCD Display
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include "keystone-k2g-evm.dts"
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	lcd0: display {
+		compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
+		label = "lcd";
+
+		backlight = <&lcd_bl>;
+
+		panel-timing {
+			clock-frequency = <9000000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <2>;
+			hback-porch = <2>;
+			hsync-len = <41>;
+			vfront-porch = <2>;
+			vback-porch = <2>;
+			vsync-len = <10>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <1>;
+		};
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+
+	lcd_bl: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 32 64 96 128 160 192 224 255>;
+		default-brightness-level = <8>;
+	};
+};
+
+&i2c1 {
+	edt-ft5306@38 {
+		status = "okay";
+		compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
+		reg = <0x38>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edt_ft5306_ts_pins>;
+
+		interrupt-parent = <&gpio1>;
+		interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
+
+		touchscreen-size-x = <480>;
+		touchscreen-size-y = <272>;
+	};
+};
+
+&k2g_pinctrl {
+	edt_ft5306_ts_pins: edt_ft5306_ts_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1364) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE3)	/* pr1_pru1_gpo16.gpio1_42 */
+		>;
+	};
+};
+
+&dpi_out {
+	remote-endpoint = <&lcd_in>;
+};
+
+&sii9022 {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 6a4657799b99..b232e3b30d76 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -81,6 +81,13 @@
 		>;
 	};
 
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
+			K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
+		>;
+	};
+
 	ecap0_pins: ecap0_pins {
 		pinctrl-single,pins = <
 			K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)	/* pr1_mdio_data.ecap0_in_apwm0_out */
@@ -114,6 +121,46 @@
 			K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart2_txd.uart2_txd */
 		>;
 	};
+
+	vout_pins: pinmux_vout_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
+			K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
+			K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
+			K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
+			K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
+			K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
+			K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
+			K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
+			K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
+			K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
+			K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
+			K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
+			K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
+			K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
+			K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
+			K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
+			K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
+			K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
+			K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
+			K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
+			K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
+			K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
+			K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
+			K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
+			K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
+			K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
+			K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
+			K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
+			K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
+		>;
+	};
+
+	sii9022_pins: sii9022_pins {
+		pinctrl-single,pins = <
+			K2G_CORE_IOPAD(0x1338) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3)      /* pr1_pru1_gpo5.gpio1_31 */
+		>;
+	};
 };
 
 &uart0 {
@@ -268,3 +315,43 @@
 	pinctrl-0 = <&uart2_pins>;
 	status = "okay";
 };
+
+&dss {
+	pinctrl-names = "default";
+	pinctrl-0 = <&vout_pins>;
+	status = "ok";
+
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&sii9022_in>;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+	clock-frequency = <400000>;
+
+	sii9022: sii9022@3b {
+		compatible = "sil,sii9022";
+		reg = <0x3b>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&sii9022_pins>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				sii9022_in: endpoint {
+					remote-endpoint = <&dpi_out>;
+				};
+			};
+		};
+	};
+};
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