[PATCH v3 4/7] arm64: dts: qcom: talos: Add QSPI support

Viken Dadhaniya
2026-04-20T06:13:26Z

The Talos (QCS615) platform includes a QSPI controller used for accessing
external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and
the QSPI controller node to enable support for this hardware.

Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 75716b4a58d6..4b67b3401615 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel {

};

+ qspi_opp_table: opp-table-qspi {
+ compatible = "operating-points-v2";
+
+ opp-60000000 {
+ opp-hz = /bits/ 64 <60000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-133250000 {
+ opp-hz = /bits/ 64 <133250000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-266500000 {
+ opp-hz = /bits/ 64 <266500000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
qup_opp_table: opp-table-qup {
compatible = "operating-points-v2";

@@ -1553,6 +1572,34 @@ tlmm: pinctrl@3100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;

+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio44";
+ function = "qspi";
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ qspi_data0123: qspi-data0123-state {
+ pins = "gpio45", "gpio46", "gpio47", "gpio49";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ qspi_clk: qspi-clk-state {
+ pins = "gpio48";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio50";
+ function = "qspi";
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup0";
@@ -3682,6 +3729,39 @@ opp-202000000 {
};
};

+ qspi: spi@88df000 {
+ compatible = "qcom,qcs615-qspi",
+ "qcom,qspi-v1";
+ reg = <0x0 0x088df000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface",
+ "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qspi-config",
+ "qspi-memory";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+
+ iommus = <&apps_smmu 0x160 0x0>;
+
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
dc_noc: interconnect@9160000 {
reg = <0x0 0x09160000 0x0 0x3200>;
compatible = "qcom,qcs615-dc-noc";

--
2.34.1