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Fri, 17 Apr 2026 07:59:31 -0700 (PDT) X-Received: by 2002:a17:902:f788:b0:2b2:d126:4e77 with SMTP id d9443c01a7336-2b5f9eaea76mr38560565ad.11.1776437971054; Fri, 17 Apr 2026 07:59:31 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab40786sm25205125ad.79.2026.04.17.07.59.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Apr 2026 07:59:30 -0700 (PDT) Message-ID: <26b71f52-3355-d4e9-f640-007123e3aba2@oss.qualcomm.com> Date: Fri, 17 Apr 2026 20:29:21 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 02/11] media: iris: Add iris vpu bus support and register it with iommu_buses Content-Language: en-US From: Vishnu Reddy To: Dmitry Baryshkov Cc: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio , Stefan Schmidt , Hans Verkuil , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev References: <20260414-glymur-v1-0-7d3d1cf57b16@oss.qualcomm.com> <20260414-glymur-v1-2-7d3d1cf57b16@oss.qualcomm.com> <5dee6da0-9170-d9e0-5ff7-f8436331c6a9@oss.qualcomm.com> In-Reply-To: <5dee6da0-9170-d9e0-5ff7-f8436331c6a9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: CvTJKZO0hBockfRT2ltAyIKv4N0nz1Uq X-Authority-Analysis: v=2.4 cv=XNoAjwhE c=1 sm=1 tr=0 ts=69e24ad4 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=mC123iS2TVYQaReKmh0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: CvTJKZO0hBockfRT2ltAyIKv4N0nz1Uq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDE1MCBTYWx0ZWRfXzrr2x69Zu6wT 144fnOCxjzZXGjN16E5pGOu9BqeXCbNH2JD5fZQKv3l3ogu2V9WN+XdGfMq5qqrrUZtMIJx8vVH SMYLBqy63nDp8L3xDzbT+SZDvYzMRAbhuWuF0vAYXCoVKPrizucPAQTk8sHKVzeKviemb8cZ4T9 i7lGuFwjzhdVn7kAJX9hxc2ehlXuhPszwUTdmIIn9xIIrK8UnLIlYmDalqC0pKcCtDLNkEsbqQE 7u8PjeAkLx5fteoxQZ+QvcNxyY2xHaWZ3WwdLqdWxAxlgH9BIWfIQBD4s2S8YSVo7kfscqA6VIW rcKeYlpn9gZlGy7fyASh4o5AChEDKiXVkX4RavJXEjxzKqmEwhOKh38LNbE5TlTowaiSe0n3jWm qKWUzYI+oHykHf3KEZ+2NfymyJObNPxbaoQQV3B19s4PNhr20gFxfYmlxnvScthcEew60N0Mbab IJAFxUb+jeLl5dKVDlw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 priorityscore=1501 suspectscore=0 spamscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170150 apologies for re-sending (earlier responses was rejected due to HTML format) On 4/17/2026 8:22 PM, Vishnu Reddy wrote: > On 4/14/2026 8:44 PM, Dmitry Baryshkov wrote: >> On Tue, Apr 14, 2026 at 10:29:58AM +0530, Vishnu Reddy wrote: >>> From: Vikash Garodia >>> >>> Add a dedicated iris VPU bus type and register it into the iommu_buses >>> list. Iris devices require their own bus so that each device can run its >>> own dma_configure() logic. >> This really tells nothing, unless one has full context about the Iris >> needs. Start by describing the issue (that the device needs to have >> multiple devices talking to describe IOMMUs / VAs for several hardware >> functions), then continue by describing what is needed from the IOMMU >> subsys. > > This series handles firmware device which do not require multiple > devices part. > given this device need for specific IOMMU configuration, I'll update > the description > accordingly. > >>> Signed-off-by: Vikash Garodia >>> Signed-off-by: Vishnu Reddy >>> --- >>> drivers/iommu/iommu.c | 4 ++++ >>> drivers/media/platform/qcom/iris/Makefile | 4 ++++ >>> drivers/media/platform/qcom/iris/iris_vpu_bus.c | 32 +++++++++++++++++++++++++ >>> include/linux/iris_vpu_bus.h | 13 ++++++++++ >> How are you supposed to merge this? Through IOMMU tree? Through venus >> tree? Can we add one single bus to the IOMMU code and use it for Iris, >> Venus, FastRPC, host1x and all other device drivers which require >> per-device DMA configuration? > > Separating out the bus definition and the Iris driver handling would > provide a > cleaner merge path. > >> Your colleagues from the FastRPC team posted a very similar code few >> weeks ago and got exactly the same feedback. Is there a reason why your >> teams don't sync on the IOMMU parts at all? > > I would admit that I missed to review that, thank you for bringing > that discussion. > FastRPC patches generalizes the handling for host1x, FastRPC and the > same can be > extended for Iris. I have left few comments there. > >>> 4 files changed, 53 insertions(+) >>> >>> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c >>> index 61c12ba78206..d8ed6ef70ecd 100644 >>> --- a/drivers/iommu/iommu.c >>> +++ b/drivers/iommu/iommu.c >>> @@ -13,6 +13,7 @@ >>> #include >>> #include >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -179,6 +180,9 @@ static const struct bus_type * const iommu_buses[] = { >>> #ifdef CONFIG_CDX_BUS >>> &cdx_bus_type, >>> #endif >>> +#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS) >>> + &iris_vpu_bus_type, >>> +#endif >>> }; >>> >>> /* >>> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile >>> index 2abbd3aeb4af..6f4052b98491 100644 >>> --- a/drivers/media/platform/qcom/iris/Makefile >>> +++ b/drivers/media/platform/qcom/iris/Makefile >>> @@ -31,3 +31,7 @@ qcom-iris-objs += iris_platform_gen1.o >>> endif >>> >>> obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o >>> + >>> +ifdef CONFIG_VIDEO_QCOM_IRIS >>> +obj-y += iris_vpu_bus.o >>> +endif >>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_bus.c b/drivers/media/platform/qcom/iris/iris_vpu_bus.c >>> new file mode 100644 >>> index 000000000000..b51bb4b82b0e >>> --- /dev/null >>> +++ b/drivers/media/platform/qcom/iris/iris_vpu_bus.c >>> @@ -0,0 +1,32 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +#include >>> +#include >>> + >>> +#include "iris_platform_common.h" >>> + >>> +static int iris_vpu_bus_dma_configure(struct device *dev) >>> +{ >>> + const u32 *f_id = dev_get_drvdata(dev); >>> + >>> + if (!f_id) >>> + return -ENODEV; >>> + >>> + return of_dma_configure_id(dev, dev->parent->of_node, true, f_id); >> I think it was discussed that this is not enough. Some of devices need >> multiple function IDs. > > In this glymur series we are following the legacy way of handling > IOMMUs and does not > require multi map. > > Thanks, > Vishnu Reddy. > >>> +} >>> + >>> +const struct bus_type iris_vpu_bus_type = { >>> + .name = "iris-vpu-bus", >>> + .dma_configure = iris_vpu_bus_dma_configure, >>> +}; >>> +EXPORT_SYMBOL_GPL(iris_vpu_bus_type); >>> + >>> +static int __init iris_vpu_bus_init(void) >>> +{ >>> + return bus_register(&iris_vpu_bus_type); >>> +} >>> + >>> +postcore_initcall(iris_vpu_bus_init); >>> diff --git a/include/linux/iris_vpu_bus.h b/include/linux/iris_vpu_bus.h >>> new file mode 100644 >>> index 000000000000..5704b226f7d6 >>> --- /dev/null >>> +++ b/include/linux/iris_vpu_bus.h >>> @@ -0,0 +1,13 @@ >>> +/* SPDX-License-Identifier: GPL-2.0-only */ >>> +/* >>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +#ifndef __IRIS_VPU_BUS_H__ >>> +#define __IRIS_VPU_BUS_H__ >>> + >>> +#if IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS) >>> +extern const struct bus_type iris_vpu_bus_type; >>> +#endif >>> + >>> +#endif /* __IRIS_VPU_BUS_H__ */ >>> >>> -- >>> 2.34.1 >>>