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"vi_sensor's" in commit message. The commit message is a bit difficult to understand (to me at least), perha= ps explain it in terms of the clock signal flow, e.g. "The CSUS clock is a = clock gate for the output clock signal primarily sourced from the VI_SENSOR= clock. This clock signal is used as an input MCLK clock for cameras." For Tegra30/114, I think this is correct. For Tegra20, I noticed that for t= he two other output clocks -- cdev1 and cdev2 -- we already are modelling t= he source clock muxing in the clock framework through clocks called cdev1_m= ux and cdev2_mux which are registered as read-only mux clocks in pinctrl-te= gra20.c. So I think the same should be done for csus -- add a csus_mux cloc= k in pinctrl-tegra20.c, and make it csus's parent. For Tegra30 and later ch= ips, these output clocks seem to have only one source clock. Thanks, Mikko >=20 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/clk/tegra/clk-tegra114.c | 7 ++++++- > drivers/clk/tegra/clk-tegra20.c | 7 ++++++- > drivers/clk/tegra/clk-tegra30.c | 7 ++++++- > 3 files changed, 18 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-teg= ra114.c > index 186b0b81c1ec..00282b0d3763 100644 > --- a/drivers/clk/tegra/clk-tegra114.c > +++ b/drivers/clk/tegra/clk-tegra114.c > @@ -691,7 +691,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] = __initdata =3D { > [tegra_clk_tsec] =3D { .dt_id =3D TEGRA114_CLK_TSEC, .present =3D true = }, > [tegra_clk_xusb_host] =3D { .dt_id =3D TEGRA114_CLK_XUSB_HOST, .present= =3D true }, > [tegra_clk_msenc] =3D { .dt_id =3D TEGRA114_CLK_MSENC, .present =3D tru= e }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA114_CLK_CSUS, .present =3D true = }, > [tegra_clk_mselect] =3D { .dt_id =3D TEGRA114_CLK_MSELECT, .present =3D= true }, > [tegra_clk_tsensor] =3D { .dt_id =3D TEGRA114_CLK_TSENSOR, .present =3D= true }, > [tegra_clk_i2s3] =3D { .dt_id =3D TEGRA114_CLK_I2S3, .present =3D true = }, > @@ -1047,6 +1046,12 @@ static __init void tegra114_periph_clk_init(void _= _iomem *clk_base, > 0, 82, periph_clk_enb_refcnt); > clks[TEGRA114_CLK_DSIB] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, > + clk_base, 0, TEGRA114_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA114_CLK_CSUS] =3D clk; > + > /* emc mux */ > clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, > ARRAY_SIZE(mux_pllmcp_clkm), > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegr= a20.c > index 2c58ce25af75..bf9a9f8ddf62 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] _= _initdata =3D { > [tegra_clk_rtc] =3D { .dt_id =3D TEGRA20_CLK_RTC, .present =3D true }, > [tegra_clk_timer] =3D { .dt_id =3D TEGRA20_CLK_TIMER, .present =3D true= }, > [tegra_clk_kbc] =3D { .dt_id =3D TEGRA20_CLK_KBC, .present =3D true }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA20_CLK_CSUS, .present =3D true }= , > [tegra_clk_vcp] =3D { .dt_id =3D TEGRA20_CLK_VCP, .present =3D true }, > [tegra_clk_bsea] =3D { .dt_id =3D TEGRA20_CLK_BSEA, .present =3D true }= , > [tegra_clk_bsev] =3D { .dt_id =3D TEGRA20_CLK_BSEV, .present =3D true }= , > @@ -807,6 +806,12 @@ static void __init tegra20_periph_clk_init(void) > clk_register_clkdev(clk, NULL, "dsi"); > clks[TEGRA20_CLK_DSI] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, > + clk_base, 0, TEGRA20_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA20_CLK_CSUS] =3D clk; > + > /* pex */ > clk =3D tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, = 70, > periph_clk_enb_refcnt); > diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegr= a30.c > index 82a8cb9545eb..ca367184e185 100644 > --- a/drivers/clk/tegra/clk-tegra30.c > +++ b/drivers/clk/tegra/clk-tegra30.c > @@ -779,7 +779,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] _= _initdata =3D { > [tegra_clk_rtc] =3D { .dt_id =3D TEGRA30_CLK_RTC, .present =3D true }, > [tegra_clk_timer] =3D { .dt_id =3D TEGRA30_CLK_TIMER, .present =3D true= }, > [tegra_clk_kbc] =3D { .dt_id =3D TEGRA30_CLK_KBC, .present =3D true }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA30_CLK_CSUS, .present =3D true }= , > [tegra_clk_vcp] =3D { .dt_id =3D TEGRA30_CLK_VCP, .present =3D true }, > [tegra_clk_bsea] =3D { .dt_id =3D TEGRA30_CLK_BSEA, .present =3D true }= , > [tegra_clk_bsev] =3D { .dt_id =3D TEGRA30_CLK_BSEV, .present =3D true }= , > @@ -1008,6 +1007,12 @@ static void __init tegra30_periph_clk_init(void) > 0, 48, periph_clk_enb_refcnt); > clks[TEGRA30_CLK_DSIA] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, > + clk_base, 0, TEGRA30_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA30_CLK_CSUS] =3D clk; > + > /* pcie */ > clk =3D tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, > 70, periph_clk_enb_refcnt); >=20