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Sat, 18 Jan 2025 08:28:16 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/14] arm64: dts: allwinner: Add Allwinner A523 .dtsi file Date: Sat, 18 Jan 2025 17:28:14 +0100 Message-ID: <2763298.mvXUDI8C0e@jernej-laptop> In-Reply-To: <20241111013033.22793-12-andre.przywara@arm.com> References: <20241111013033.22793-1-andre.przywara@arm.com> <20241111013033.22793-12-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 11. november 2024 ob 02:30:30 Srednjeevropski standardni = =C4=8Das je Andre Przywara napisal(a): > The Allwinner A523, and its siblings A527 and T527, which share the same > die, are a new family of SoCs introduced in 2023. They features eight > Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and > USB 3.0 controller. >=20 > Add the basic SoC devicetree .dtsi for the chip, describing the > fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl. > Also some other peripherals are fully compatible with previous IP, so > add the USB and MMC nodes as well. > The other peripherals will be added in the future, once we understand > their compatibility and DT requirements. >=20 > Signed-off-by: Andre Przywara > --- > .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 386 ++++++++++++++++++ > 1 file changed, 386 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/= boot/dts/allwinner/sun55i-a523.dtsi > new file mode 100644 > index 0000000000000..96072cea10da4 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi > @@ -0,0 +1,386 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +// Copyright (C) 2023-2024 Arm Ltd. > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent =3D <&gic>; > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + > + cpus { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + cpu0: cpu@0 { > + compatible =3D "arm,cortex-a55"; > + device_type =3D "cpu"; > + reg =3D <0x000>; > + }; > + }; > + > + ext_osc32k: ext-osc32k-clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <32768>; > + clock-output-names =3D "ext_osc32k"; > + }; osc32k should be part of the board DT. It's not mandatory, and some boards, at least with older generations of SoCs, don't have it. Best regards, Jernej > + > + osc24M: osc24M-clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <24000000>; > + clock-output-names =3D "osc24M"; > + }; > + > + pmu { > + compatible =3D "arm,cortex-a55-pmu"; > + interrupts =3D ; > + }; > + > + timer { > + compatible =3D "arm,armv8-timer"; > + arm,no-tick-in-suspend; > + interrupts =3D , > + , > + , > + ; > + }; > + > + soc { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges =3D <0x0 0x0 0x0 0x40000000>; > + > + pio: pinctrl@2000000 { > + compatible =3D "allwinner,sun55i-a523-pinctrl"; > + reg =3D <0x2000000 0x800>; > + interrupts =3D , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks =3D <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names =3D "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells =3D <3>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + > + mmc0_pins: mmc0-pins { > + pins =3D "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; > + allwinner,pinmux =3D <2>; > + function =3D "mmc0"; > + drive-strength =3D <30>; > + bias-pull-up; > + }; > + > + /omit-if-no-ref/ > + mmc1_pins: mmc1-pins { > + pins =3D "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; > + allwinner,pinmux =3D <2>; > + function =3D "mmc1"; > + drive-strength =3D <30>; > + bias-pull-up; > + }; > + > + mmc2_pins: mmc2-pins { > + pins =3D "PC1" ,"PC5", "PC6", "PC8", "PC9", > + "PC10", "PC11", "PC13", "PC14", "PC15", > + "PC16"; > + allwinner,pinmux =3D <3>; > + function =3D "mmc2"; > + drive-strength =3D <30>; > + bias-pull-up; > + }; > + > + uart0_pb_pins: uart0-pb-pins { > + pins =3D "PB9", "PB10"; > + allwinner,pinmux =3D <2>; > + function =3D "uart0"; > + }; > + }; > + > + ccu: clock@2001000 { > + compatible =3D "allwinner,sun55i-a523-ccu"; > + reg =3D <0x02001000 0x1000>; > + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; > + clock-names =3D "hosc", "losc", "iosc"; > + #clock-cells =3D <1>; > + #reset-cells =3D <1>; > + }; > + > + mmc0: mmc@4020000 { > + compatible =3D "allwinner,sun55i-a523-mmc", > + "allwinner,sun20i-d1-mmc"; > + reg =3D <0x04020000 0x1000>; > + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; > + clock-names =3D "ahb", "mmc"; > + resets =3D <&ccu RST_BUS_MMC0>; > + reset-names =3D "ahb"; > + interrupts =3D ; > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&mmc0_pins>; > + status =3D "disabled"; > + > + max-frequency =3D <150000000>; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + cap-sdio-irq; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + mmc2: mmc@4022000 { > + compatible =3D "allwinner,sun55i-a523-mmc", > + "allwinner,sun20i-d1-mmc"; > + reg =3D <0x04022000 0x1000>; > + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; > + clock-names =3D "ahb", "mmc"; > + resets =3D <&ccu RST_BUS_MMC2>; > + reset-names =3D "ahb"; > + interrupts =3D ; > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&mmc2_pins>; > + status =3D "disabled"; > + > + max-frequency =3D <150000000>; > + cap-sd-highspeed; > + cap-mmc-highspeed; > + cap-sdio-irq; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + wdt: watchdog@2050000 { > + compatible =3D "allwinner,sun55i-a523-wdt"; > + reg =3D <0x2050000 0x20>; > + interrupts =3D ; > + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>; > + clock-names =3D "hosc", "losc"; > + status =3D "okay"; > + }; > + > + uart0: serial@2500000 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x02500000 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&ccu CLK_BUS_UART0>; > + resets =3D <&ccu RST_BUS_UART0>; > + status =3D "disabled"; > + }; > + > + i2c0: i2c@2502000 { > + compatible =3D "allwinner,sun55i-a523-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg =3D <0x2502000 0x400>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_I2C0>; > + resets =3D <&ccu RST_BUS_I2C0>; > + status =3D "disabled"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + gic: interrupt-controller@3400000 { > + compatible =3D "arm,gic-v3"; > + #address-cells =3D <1>; > + #interrupt-cells =3D <3>; > + #size-cells =3D <1>; > + ranges; > + interrupt-controller; > + reg =3D <0x3400000 0x10000>, > + <0x3460000 0x100000>; > + interrupts =3D ; > + dma-noncoherent; > + > + its: msi-controller@3440000 { > + compatible =3D "arm,gic-v3-its"; > + reg =3D <0x3440000 0x20000>; > + msi-controller; > + #msi-cells =3D <1>; > + dma-noncoherent; > + }; > + }; > + > + usb_otg: usb@4100000 { > + compatible =3D "allwinner,sun55i-a523-musb", > + "allwinner,sun8i-a33-musb"; > + reg =3D <0x4100000 0x400>; > + interrupts =3D ; > + interrupt-names =3D "mc"; > + clocks =3D <&ccu CLK_BUS_OTG>; > + resets =3D <&ccu RST_BUS_OTG>; > + extcon =3D <&usbphy 0>; > + phys =3D <&usbphy 0>; > + phy-names =3D "usb"; > + status =3D "disabled"; > + }; > + > + usbphy: phy@4100400 { > + compatible =3D "allwinner,sun55i-a523-usb-phy", > + "allwinner,sun20i-d1-usb-phy"; > + reg =3D <0x4100400 0x100>, > + <0x4101800 0x100>, > + <0x4200800 0x100>; > + reg-names =3D "phy_ctrl", > + "pmu0", > + "pmu1"; > + clocks =3D <&osc24M>, > + <&osc24M>; > + clock-names =3D "usb0_phy", > + "usb1_phy"; > + resets =3D <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY1>; > + reset-names =3D "usb0_reset", > + "usb1_reset"; > + status =3D "disabled"; > + #phy-cells =3D <1>; > + }; > + > + ehci0: usb@4101000 { > + compatible =3D "allwinner,sun55i-a523-ehci", > + "generic-ehci"; > + reg =3D <0x4101000 0x100>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_BUS_EHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets =3D <&ccu RST_BUS_OHCI0>, > + <&ccu RST_BUS_EHCI0>; > + phys =3D <&usbphy 0>; > + phy-names =3D "usb"; > + status =3D "disabled"; > + }; > + > + ohci0: usb@4101400 { > + compatible =3D "allwinner,sun55i-a523-ohci", > + "generic-ohci"; > + reg =3D <0x4101400 0x100>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets =3D <&ccu RST_BUS_OHCI0>; > + phys =3D <&usbphy 0>; > + phy-names =3D "usb"; > + status =3D "disabled"; > + }; > + > + ehci1: usb@4200000 { > + compatible =3D "allwinner,sun55i-a523-ehci", > + "generic-ehci"; > + reg =3D <0x4200000 0x100>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_BUS_EHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets =3D <&ccu RST_BUS_OHCI1>, > + <&ccu RST_BUS_EHCI1>; > + phys =3D <&usbphy 1>; > + phy-names =3D "usb"; > + status =3D "disabled"; > + }; > + > + ohci1: usb@4200400 { > + compatible =3D "allwinner,sun55i-a523-ohci", > + "generic-ohci"; > + reg =3D <0x4200400 0x100>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets =3D <&ccu RST_BUS_OHCI1>; > + phys =3D <&usbphy 1>; > + phy-names =3D "usb"; > + status =3D "disabled"; > + }; > + > + r_ccu: clock-controller@7010000 { > + compatible =3D "allwinner,sun55i-a523-r-ccu"; > + reg =3D <0x7010000 0x250>; > + clocks =3D <&osc24M>, > + <&rtc CLK_OSC32K>, > + <&rtc CLK_IOSC>, > + <&ccu CLK_PLL_PERIPH0_200M>, > + <&ccu CLK_PLL_AUDIO0_4X>; > + clock-names =3D "hosc", > + "losc", > + "iosc", > + "pll-periph", > + "pll-audio"; > + #clock-cells =3D <1>; > + #reset-cells =3D <1>; > + }; > + > + nmi_intc: interrupt-controller@7010320 { > + compatible =3D "allwinner,sun55i-a523-nmi", > + "allwinner,sun9i-a80-nmi"; > + reg =3D <0x07010320 0xc>; > + interrupt-controller; > + #interrupt-cells =3D <2>; > + interrupts =3D ; > + }; > + > + r_pio: pinctrl@7022000 { > + compatible =3D "allwinner,sun55i-a523-r-pinctrl"; > + reg =3D <0x7022000 0x800>; > + interrupts =3D , > + ; > + clocks =3D <&r_ccu CLK_R_APB0>, > + <&osc24M>, > + <&rtc CLK_OSC32K>; > + clock-names =3D "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells =3D <3>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + > + r_i2c_pins: r-i2c-pins { > + pins =3D "PL0" ,"PL1"; > + allwinner,pinmux =3D <2>; > + function =3D "r_i2c0"; > + }; > + }; > + > + r_i2c0: i2c@7081400 { > + compatible =3D "allwinner,sun55i-a523-i2c", > + "allwinner,sun8i-v536-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg =3D <0x07081400 0x400>; > + interrupts =3D ; > + clocks =3D <&r_ccu CLK_BUS_R_I2C0>; > + resets =3D <&r_ccu RST_BUS_R_I2C0>; > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&r_i2c_pins>; > + status =3D "disabled"; > + > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; > + > + rtc: rtc@7090000 { > + compatible =3D "allwinner,sun55i-a523-rtc", > + "allwinner,sun50i-r329-rtc"; > + reg =3D <0x7090000 0x400>; > + interrupts =3D ; > + clocks =3D <&r_ccu CLK_BUS_R_RTC>, > + <&osc24M>, > + <&r_ccu CLK_R_AHB>; > + clock-names =3D "bus", "hosc", "ahb"; > + #clock-cells =3D <1>; > + }; > + }; > +}; >=20