[PATCH 0/4] rockchip: Add efuse support for RK3368 SoCs

[PATCH 0/4] rockchip: Add efuse support for RK3368 SoCs

[Romain Perier]

This set of patches exports the right clocks, add required functions
and data, and definition for enabling and supporting eFuse on RK3368
SoCs.

Romain Perier (4):
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  nvmem: rockchip: add support for RK3368
  arm64: dts: rockchip: add efuse for RK3368 SoCs

 .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +
 arch/arm64/boot/dts/rockchip/rk3368.dtsi           | 14 ++++
 drivers/clk/rockchip/clk-rk3368.c                  |  2 +-
 drivers/nvmem/rockchip-efuse.c                     | 80 ++++++++++++++++++++++
 include/dt-bindings/clock/rk3368-cru.h             |  1 +
 5 files changed, 97 insertions(+), 1 deletion(-)

-- 
2.11.0

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[PATCH 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

[Romain Perier]

Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
 include/dt-bindings/clock/rk3368-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index aeb83e581a11..a0063ed7284a 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -156,6 +156,7 @@
 #define PCLK_ISP		366
 #define PCLK_VIP		367
 #define PCLK_WDT		368
+#define PCLK_EFUSE256		369
 
 /* hclk gates */
 #define HCLK_SFC		448
-- 
2.11.0

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[PATCH 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs

[Romain Perier]

This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.

Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
-	GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
 	GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
 
 	/*
-- 
2.11.0

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[PATCH 4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

[Romain Perier]

This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3039c2da533e..cca2ce1705b3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -569,6 +569,20 @@
 		};
 	};
 
+	efuse: efuse@ffb00000 {
+		compatible = "rockchip,rk3368-efuse";
+		reg = <0x0 0xffb00000 0x0 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu-leakage@17 {
+			reg = <0x17 0x1>;
+		};
+		temp_adjust: temp-adjust@1f {
+			reg = <0x1f 0x1>;
+		};
+	};
+
 	tsadc: tsadc@ff280000 {
 		compatible = "rockchip,rk3368-tsadc";
 		reg = <0x0 0xff280000 0x0 0x100>;
-- 
2.11.0

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[PATCH 3/4] nvmem: rockchip: add support for RK3368

[Romain Perier]

This adds the necessary functions and data for handling support on RK3368
SoCs.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +
 drivers/nvmem/rockchip-efuse.c                     | 80 ++++++++++++++++++++++
 2 files changed, 81 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
index 1ff02afdc55a..60bec4782806 100644
--- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
@@ -6,6 +6,7 @@ Required properties:
   - "rockchip,rk3188-efuse" - for RK3188 SoCs.
   - "rockchip,rk3228-efuse" - for RK3228 SoCs.
   - "rockchip,rk3288-efuse" - for RK3288 SoCs.
+  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
   - "rockchip,rk3399-efuse" - for RK3399 SoCs.
 - reg: Should contain the registers location and exact eFuse size
 - clocks: Should be the clock id of eFuse
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index 63e3eb55f3ac..4e11f251035f 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -14,6 +14,7 @@
  * more details.
  */
 
+#include <linux/arm-smccc.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/device.h>
@@ -46,9 +47,17 @@
 #define REG_EFUSE_CTRL		0x0000
 #define REG_EFUSE_DOUT		0x0004
 
+/* SMC function IDs for SiP Service queries */
+#define ROCKCHIP_SIP_ACCESS_REG	0x82000002
+
+/* SIP access registers: read or write */
+#define ROCKCHIP_SIP_SECURE_REG_RD	0x0
+#define ROCKCHIP_SIP_SECURE_REG_WR	0x1
+
 struct rockchip_efuse_chip {
 	struct device *dev;
 	void __iomem *base;
+	phys_addr_t phys;
 	struct clk *clk;
 };
 
@@ -92,6 +101,72 @@ static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
 	return 0;
 }
 
+static u32 smc_reg_read(u32 addr_phy)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, 0, addr_phy,
+		      ROCKCHIP_SIP_SECURE_REG_RD, 0, 0, 0, 0, &res);
+	if (res.a0)
+		pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0,
+		       addr_phy);
+	return res.a1;
+}
+
+static u32 smc_reg_write(u32 addr_phy, u32 val)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, val, addr_phy,
+		      ROCKCHIP_SIP_SECURE_REG_WR, 0, 0, 0, 0, &res);
+	if (res.a0)
+		pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0,
+                       addr_phy);
+	return res.a0;
+}
+
+static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,
+				      void *val, size_t bytes)
+{
+	struct rockchip_efuse_chip *efuse = context;
+	u8 *buf = val;
+	int ret;
+
+	ret = clk_prepare_enable(efuse->clk);
+	if (ret < 0) {
+		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
+		return ret;
+	}
+
+	smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
+	udelay(1);
+	while (bytes--) {
+		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
+			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &
+			      (~(RK3288_A_MASK << RK3288_A_SHIFT)));
+		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
+			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |
+			      ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT));
+
+		udelay(1);
+		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
+			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |
+			      RK3288_STROBE);
+		udelay(1);
+		*buf++ = smc_reg_read(efuse->phys + REG_EFUSE_DOUT);
+		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
+			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &
+			      (~RK3288_STROBE));
+		udelay(1);
+	}
+
+	/* Switch to standby mode */
+	smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
+
+	clk_disable_unprepare(efuse->clk);
+	return 0;
+}
+
 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
 				      void *val, size_t bytes)
 {
@@ -178,6 +253,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
 		.data = (void *)&rockchip_rk3288_efuse_read,
 	},
 	{
+		.compatible = "rockchip,rk3368-efuse",
+		.data = (void *)&rockchip_rk3368_efuse_read,
+	},
+	{
 		.compatible = "rockchip,rk3399-efuse",
 		.data = (void *)&rockchip_rk3399_efuse_read,
 	},
@@ -205,6 +284,7 @@ static int rockchip_efuse_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	efuse->phys = res->start;
 	efuse->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(efuse->base))
 		return PTR_ERR(efuse->base);
-- 
2.11.0

Re: [PATCH 3/4] nvmem: rockchip: add support for RK3368

[Heiko Stübner]

Hi Romain,

Am Montag, 28. August 2017, 14:16:03 CEST schrieb Romain Perier:
> This adds the necessary functions and data for handling support on RK3368
> SoCs.

Would need a lot more explanation regarding the special use for
SMC calls for efuse access.


> Signed-off-by: Romain Perier <romain.perier@collabora.com>
> ---
>  .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +
>  drivers/nvmem/rockchip-efuse.c                     | 80
> ++++++++++++++++++++++ 2 files changed, 81 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt index
> 1ff02afdc55a..60bec4782806 100644
> --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> @@ -6,6 +6,7 @@ Required properties:
>    - "rockchip,rk3188-efuse" - for RK3188 SoCs.
>    - "rockchip,rk3228-efuse" - for RK3228 SoCs.
>    - "rockchip,rk3288-efuse" - for RK3288 SoCs.
> +  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
>    - "rockchip,rk3399-efuse" - for RK3399 SoCs.
>  - reg: Should contain the registers location and exact eFuse size
>  - clocks: Should be the clock id of eFuse
> diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
> index 63e3eb55f3ac..4e11f251035f 100644
> --- a/drivers/nvmem/rockchip-efuse.c
> +++ b/drivers/nvmem/rockchip-efuse.c
> @@ -14,6 +14,7 @@
>   * more details.
>   */
> 
> +#include <linux/arm-smccc.h>
>  #include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/device.h>
> @@ -46,9 +47,17 @@
>  #define REG_EFUSE_CTRL		0x0000
>  #define REG_EFUSE_DOUT		0x0004
> 
> +/* SMC function IDs for SiP Service queries */
> +#define ROCKCHIP_SIP_ACCESS_REG	0x82000002
> +
> +/* SIP access registers: read or write */
> +#define ROCKCHIP_SIP_SECURE_REG_RD	0x0
> +#define ROCKCHIP_SIP_SECURE_REG_WR	0x1
> +

Going through SMC calls does _not_ look right.

For one even the newest rk3399 can handle its efuse using
regular means, so the rk3368 being  somehow special feels strange.

And even if that is a sanctioned approach, the smc calls are not
part of the upstream arm-trusted-firmware at this moment
and we definitly don't want to codify private unreviewed
interfaces between the mainline kernel and firmware.

See empty smc calls for rk3368 on [0] and used smc-calls on the rk3399
in [1] and I also didn't see any open pull request for something like this.


Heiko

[0] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/rk3368/plat_sip_calls.c
[1] https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/rk3399/plat_sip_calls.c

Re: [3/4] nvmem: rockchip: add support for RK3368

[Philipp Tomsich]

On Mon, 28 Aug 2017, Romain Perier wrote:

> This adds the necessary functions and data for handling support on RK3368
> SoCs.
>
> Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +
> drivers/nvmem/rockchip-efuse.c                     | 80 ++++++++++++++++++++++
> 2 files changed, 81 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> index 1ff02afdc55a..60bec4782806 100644
> --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
> @@ -6,6 +6,7 @@ Required properties:
>   - "rockchip,rk3188-efuse" - for RK3188 SoCs.
>   - "rockchip,rk3228-efuse" - for RK3228 SoCs.
>   - "rockchip,rk3288-efuse" - for RK3288 SoCs.
> +  - "rockchip,rk3368-efuse" - for RK3368 SoCs.
>   - "rockchip,rk3399-efuse" - for RK3399 SoCs.
> - reg: Should contain the registers location and exact eFuse size
> - clocks: Should be the clock id of eFuse
> diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
> index 63e3eb55f3ac..4e11f251035f 100644
> --- a/drivers/nvmem/rockchip-efuse.c
> +++ b/drivers/nvmem/rockchip-efuse.c
> @@ -14,6 +14,7 @@
>  * more details.
>  */
>
> +#include <linux/arm-smccc.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/device.h>
> @@ -46,9 +47,17 @@
> #define REG_EFUSE_CTRL		0x0000
> #define REG_EFUSE_DOUT		0x0004
>
> +/* SMC function IDs for SiP Service queries */
> +#define ROCKCHIP_SIP_ACCESS_REG	0x82000002
> +
> +/* SIP access registers: read or write */
> +#define ROCKCHIP_SIP_SECURE_REG_RD	0x0
> +#define ROCKCHIP_SIP_SECURE_REG_WR	0x1
> +
> struct rockchip_efuse_chip {
> 	struct device *dev;
> 	void __iomem *base;
> +	phys_addr_t phys;
> 	struct clk *clk;
> };
>
> @@ -92,6 +101,72 @@ static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
> 	return 0;
> }
>
> +static u32 smc_reg_read(u32 addr_phy)
> +{
> +	struct arm_smccc_res res;
> +
> +	arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, 0, addr_phy,
> +		      ROCKCHIP_SIP_SECURE_REG_RD, 0, 0, 0, 0, &res);
> +	if (res.a0)
> +		pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0,
> +		       addr_phy);
> +	return res.a1;
> +}
> +
> +static u32 smc_reg_write(u32 addr_phy, u32 val)
> +{
> +	struct arm_smccc_res res;
> +
> +	arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, val, addr_phy,
> +		      ROCKCHIP_SIP_SECURE_REG_WR, 0, 0, 0, 0, &res);
> +	if (res.a0)
> +		pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0,
> +                       addr_phy);
> +	return res.a0;
> +}

I am not too happy with the SIP_SECURE_REG_RD/WR interfaces, as this opens 
an unauthenticated path from the non-secure world into the secure world.

> +
> +static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,
> +				      void *val, size_t bytes)
> +{
> +	struct rockchip_efuse_chip *efuse = context;
> +	u8 *buf = val;
> +	int ret;
> +
> +	ret = clk_prepare_enable(efuse->clk);
> +	if (ret < 0) {
> +		dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
> +		return ret;
> +	}
> +
> +	smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);
> +	udelay(1);
> +	while (bytes--) {
> +		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
> +			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &
> +			      (~(RK3288_A_MASK << RK3288_A_SHIFT)));
> +		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
> +			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |
> +			      ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT));
> +
> +		udelay(1);
> +		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
> +			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |
> +			      RK3288_STROBE);
> +		udelay(1);
> +		*buf++ = smc_reg_read(efuse->phys + REG_EFUSE_DOUT);
> +		smc_reg_write(efuse->phys + REG_EFUSE_CTRL,
> +			      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &
> +			      (~RK3288_STROBE));
> +		udelay(1);
> +	}
> +
> +	/* Switch to standby mode */
> +	smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);
> +
> +	clk_disable_unprepare(efuse->clk);
> +	return 0;
> +}
> +
> static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
> 				      void *val, size_t bytes)
> {
> @@ -178,6 +253,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
> 		.data = (void *)&rockchip_rk3288_efuse_read,
> 	},
> 	{
> +		.compatible = "rockchip,rk3368-efuse",
> +		.data = (void *)&rockchip_rk3368_efuse_read,
> +	},
> +	{
> 		.compatible = "rockchip,rk3399-efuse",
> 		.data = (void *)&rockchip_rk3399_efuse_read,
> 	},

Both the 3368 and 3399 have two eFuse blocks: one is the 'secure' eFuse
whereas the other is the 'non-secure' eFuse... for the 'secure' eFuse, 
there is no other way to access the fuses than in EL3. However, the 
non-secure eFuse access is configurable via SGRF.

In other words: SMC calls would be necessary for accesses to the secure
eFuse block only.

Note that the DTS released in Rockchip's github account has nvmem point
to 0xffb00000, which is efuse_256 (which is the 'non-secure' block).  I 
have successfully read this on the RK3368 from the U-Boot commandline 
using 'mw.l' and 'md.l' to the control registers, so the SMC call should 
not be necessary.

The same is also true for the RK3399, where we read the non-secure fuse 
block in U-Boot. So the SMC interface shouldn't be needed there.

> @@ -205,6 +284,7 @@ static int rockchip_efuse_probe(struct platform_device *pdev)
> 		return -ENOMEM;
>
> 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	efuse->phys = res->start;
> 	efuse->base = devm_ioremap_resource(&pdev->dev, res);
> 	if (IS_ERR(efuse->base))
> 		return PTR_ERR(efuse->base);
>

Re: [PATCH 3/4] nvmem: rockchip: add support for RK3368

[Rob Herring]

On Mon, Aug 28, 2017 at 02:16:03PM +0200, Romain Perier wrote:
> This adds the necessary functions and data for handling support on RK3368
> SoCs.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>
> ---
>  .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +

For the binding only:

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/nvmem/rockchip-efuse.c                     | 80 ++++++++++++++++++++++
>  2 files changed, 81 insertions(+)