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[2003:f6:ef10:f100:a045:a7a7:11d0:8676]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d652ad17d7sm4193524a12.25.2024.12.17.03.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 03:48:04 -0800 (PST) Message-ID: <27a8b987881eedc538afb6eaf300bc7909fb85b9.camel@gmail.com> Subject: Re: [PATCH v6 10/17] iio: adc: ad7944: don't use storagebits for sizing From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?ISO-8859-1?Q?S=E1?= Cc: Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org Date: Tue, 17 Dec 2024 12:52:35 +0100 In-Reply-To: <20241211-dlech-mainline-spi-engine-offload-2-v6-10-88ee574d5d03@baylibre.com> References: <20241211-dlech-mainline-spi-engine-offload-2-v6-0-88ee574d5d03@baylibre.com> <20241211-dlech-mainline-spi-engine-offload-2-v6-10-88ee574d5d03@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-12-11 at 14:54 -0600, David Lechner wrote: > Replace use of storagebits with realbits for determining the number of > bytes needed for SPI transfers. >=20 > When adding SPI offload support, storagebits will no longer be > guaranteed to be the "best fit" for 16-bit chips so we can no longer > rely on storagebits being the correct size expected by the SPI > framework. Instead, derive the correct size from realbits since it will > always be correct even when SPI offloads are used. >=20 > Signed-off-by: David Lechner > --- Reviewed-vy: Nuno Sa > v6 changes: none >=20 > v5 changes: none >=20 > v4 changes: new patch in v4 > --- > =C2=A0drivers/iio/adc/ad7944.c | 16 +++++++++------- > =C2=A01 file changed, 9 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/iio/adc/ad7944.c b/drivers/iio/adc/ad7944.c > index > a5aea4e9f1a7bdd8ca10f9f4580ad3216ddcdfcb..6d1202bd55a013b092ff803f2065fd1= 28dfa > 9bdd 100644 > --- a/drivers/iio/adc/ad7944.c > +++ b/drivers/iio/adc/ad7944.c > @@ -98,6 +98,9 @@ struct ad7944_chip_info { > =C2=A0 const struct iio_chan_spec channels[2]; > =C2=A0}; > =C2=A0 > +/* get number of bytes for SPI xfer */ > +#define AD7944_SPI_BYTES(scan_type) ((scan_type).realbits > 16 ? 4 : 2) > + > =C2=A0/* > =C2=A0 * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a spe= cific chip > =C2=A0 * @_name: The name of the chip > @@ -164,7 +167,7 @@ static int ad7944_3wire_cs_mode_init_msg(struct devic= e > *dev, struct ad7944_adc * > =C2=A0 > =C2=A0 /* Then we can read the data during the acquisition phase */ > =C2=A0 xfers[2].rx_buf =3D &adc->sample.raw; > - xfers[2].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); > + xfers[2].len =3D AD7944_SPI_BYTES(chan->scan_type); > =C2=A0 xfers[2].bits_per_word =3D chan->scan_type.realbits; > =C2=A0 > =C2=A0 spi_message_init_with_transfers(&adc->msg, xfers, 3); > @@ -193,7 +196,7 @@ static int ad7944_4wire_mode_init_msg(struct device *= dev, > struct ad7944_adc *adc > =C2=A0 xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; > =C2=A0 > =C2=A0 xfers[1].rx_buf =3D &adc->sample.raw; > - xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); > + xfers[1].len =3D AD7944_SPI_BYTES(chan->scan_type); > =C2=A0 xfers[1].bits_per_word =3D chan->scan_type.realbits; > =C2=A0 > =C2=A0 spi_message_init_with_transfers(&adc->msg, xfers, 2); > @@ -228,7 +231,7 @@ static int ad7944_chain_mode_init_msg(struct device *= dev, > struct ad7944_adc *adc > =C2=A0 xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; > =C2=A0 > =C2=A0 xfers[1].rx_buf =3D adc->chain_mode_buf; > - xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits) * > n_chain_dev; > + xfers[1].len =3D AD7944_SPI_BYTES(chan->scan_type) * n_chain_dev; > =C2=A0 xfers[1].bits_per_word =3D chan->scan_type.realbits; > =C2=A0 > =C2=A0 spi_message_init_with_transfers(&adc->msg, xfers, 2); > @@ -274,12 +277,12 @@ static int ad7944_single_conversion(struct ad7944_a= dc > *adc, > =C2=A0 return ret; > =C2=A0 > =C2=A0 if (adc->spi_mode =3D=3D AD7944_SPI_MODE_CHAIN) { > - if (chan->scan_type.storagebits > 16) > + if (chan->scan_type.realbits > 16) > =C2=A0 *val =3D ((u32 *)adc->chain_mode_buf)[chan- > >scan_index]; > =C2=A0 else > =C2=A0 *val =3D ((u16 *)adc->chain_mode_buf)[chan- > >scan_index]; > =C2=A0 } else { > - if (chan->scan_type.storagebits > 16) > + if (chan->scan_type.realbits > 16) > =C2=A0 *val =3D adc->sample.raw.u32; > =C2=A0 else > =C2=A0 *val =3D adc->sample.raw.u16; > @@ -409,8 +412,7 @@ static int ad7944_chain_mode_alloc(struct device *dev= , > =C2=A0 /* 1 word for each voltage channel + aligned u64 for timestamp */ > =C2=A0 > =C2=A0 chain_mode_buf_size =3D ALIGN(n_chain_dev * > - BITS_TO_BYTES(chan[0].scan_type.storagebits), sizeof(u64)) > - + sizeof(u64); > + AD7944_SPI_BYTES(chan[0].scan_type), sizeof(u64)) + > sizeof(u64); > =C2=A0 buf =3D devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL); > =C2=A0 if (!buf) > =C2=A0 return -ENOMEM; >=20