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Mon, 04 Jul 2022 05:39:48 -0700 (PDT) Received: from [192.168.1.52] ([84.20.121.239]) by smtp.gmail.com with ESMTPSA id p11-20020a056512234b00b0047f6b4a53cdsm5104577lfu.172.2022.07.04.05.39.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Jul 2022 05:39:47 -0700 (PDT) Message-ID: <27c8f7b1-c308-89c2-54be-2d6c1a5527b8@linaro.org> Date: Mon, 4 Jul 2022 14:39:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v1 16/16] arm64: dts: mt8195: Add display node for vdosys0 Content-Language: en-US To: Tinghan Shen , Yong Wu , Joerg Roedel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , AngeloGioacchino Del Regno , Enric Balletbo i Serra , Weiyi Lu Cc: iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, "Jason-JH.Lin" References: <20220704100028.19932-1-tinghan.shen@mediatek.com> <20220704100028.19932-17-tinghan.shen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220704100028.19932-17-tinghan.shen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 04/07/2022 12:00, Tinghan Shen wrote: > From: "Jason-JH.Lin" > > Add display node for vdosys0 of mt8195. > > Signed-off-by: Jason-JH.Lin > Signed-off-by: Tinghan Shen > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 109 +++++++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index 724c6ca837b6..faea8ef33e5a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -1961,6 +1961,7 @@ > vdosys0: syscon@1c01a000 { > compatible = "mediatek,mt8195-mmsys", "syscon"; > reg = <0 0x1c01a000 0 0x1000>; > + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; > #clock-cells = <1>; > }; > > @@ -1976,6 +1977,114 @@ > power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > }; > > + ovl0: ovl@1c000000 { > + compatible = "mediatek,mt8195-disp-ovl", > + "mediatek,mt8183-disp-ovl"; > + reg = <0 0x1c000000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; > + }; > + > + rdma0: rdma@1c002000 { > + compatible = "mediatek,mt8195-disp-rdma"; > + reg = <0 0x1c002000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; > + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; > + }; > + > + color0: color@1c003000 { > + compatible = "mediatek,mt8195-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1c003000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; > + }; > + > + ccorr0: ccorr@1c004000 { > + compatible = "mediatek,mt8195-disp-ccorr", > + "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1c004000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; > + }; > + > + aal0: aal@1c005000 { > + compatible = "mediatek,mt8195-disp-aal", > + "mediatek,mt8183-disp-aal"; > + reg = <0 0x1c005000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; > + }; > + > + gamma0: gamma@1c006000 { > + compatible = "mediatek,mt8195-disp-gamma", > + "mediatek,mt8183-disp-gamma"; > + reg = <0 0x1c006000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; > + }; > + > + dither0: dither@1c007000 { > + compatible = "mediatek,mt8195-disp-dither", > + "mediatek,mt8183-disp-dither"; > + reg = <0 0x1c007000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; > + }; > + > + dsc0: dsc@1c009000 { > + compatible = "mediatek,mt8195-disp-dsc"; > + reg = <0 0x1c009000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; > + }; > + > + merge0: merge0@1c014000 { Generic node name. > + compatible = "mediatek,mt8195-disp-merge"; > + reg = <0 0x1c014000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; > + mediatek,gce-client-reg = > + <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; > + }; > + > + mutex: mutex0@1c016000 { Generic node name. > + compatible = "mediatek,mt8195-disp-mutex"; > + reg = <0 0x1c016000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; > + mediatek,gce-events = > + ; > + }; > + > larb0: larb@1c018000 { > compatible = "mediatek,mt8195-smi-larb"; > reg = <0 0x1c018000 0 0x1000>; Best regards, Krzysztof