Re: [PATCH RFC v2 4/6] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 4/8/2026 2:44 AM, Akhil P Oommen wrote:
> On 4/3/2026 4:39 AM, Alexander Koskovich wrote:
>> A8XX GPUs have two sets of protect registers: 64 global slots and 16
>> pipe specific slots. The last-span-unbound feature is only available
>> on pipe protect registers, and should always target pipe slot 15.
>>
>> This matches the downstream driver which hardcodes pipe slot 15 for
>> all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on
>> A810.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> 
> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> 
> -Akhil
> 
>> ---
>>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++----
>>  1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> index 8b4b022d9a6b..102d5e751536 100644
>> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
>> @@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu)
>>  	}
>>  
>>  	/*
>> -	 * Last span feature is only supported on PIPE specific register.
>> -	 * So update those here
>> +	 * Last span setting is only being applied to the last pipe specific
>> +	 * register. Hence duplicate the last span from protect reg into the
>> +	 * BR and BV protect reg pipe 15.

Not sure why you modified the comment. The original comment is accurate.
LS feature is present only in the last PIPE specific protect register.

-Akhil.

>>  	 */
>> -	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
>> -	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
>> +	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
>> +	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
>>  
>>  	a8xx_aperture_clear(gpu);
>>  }
>>
>