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Mon, 13 Oct 2025 07:58:12 +0200 (CEST) From: Alexander Stein To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Li Jun , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Xu Yang , Frank Li , Xu Yang Subject: Re: [PATCH v2 3/4] phy: fsl-imx8mq-usb: support alternate reference clock Date: Mon, 13 Oct 2025 07:58:12 +0200 Message-ID: <2805917.mvXUDI8C0e@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20251010-usb-phy-alt-clk-support-v2-3-af4b78bb4ae8@nxp.com> References: <20251010-usb-phy-alt-clk-support-v2-0-af4b78bb4ae8@nxp.com> <20251010-usb-phy-alt-clk-support-v2-3-af4b78bb4ae8@nxp.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; 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Oktober 2025, 13:01:12 CEST schrieb Xu Yang: > This phy supports both 24MHz and 100MHz clock inputs. By default it's > using XTAL 24MHz and the 100MHz clock is a alternate reference clock. > Add supports to use alternate reference clock in case 24MHz clock > can't work well. This driver supports imx8mx and imx8mp as well. Do these SoC also support the alternative clock? Best regards Alexander > > Reviewed-by: Frank Li > Signed-off-by: Xu Yang > > --- > Changes in v2: > - add Rb tag > --- > drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c > index b94f242420fc733cd75abef8ba1cd4f59ac18eb5..ad8a55012e42f2c15496955d00c6d5fd85c5beb2 100644 > --- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c > @@ -16,6 +16,7 @@ > #define PHY_CTRL0_REF_SSP_EN BIT(2) > #define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) > #define PHY_CTRL0_FSEL_24M 0x2a > +#define PHY_CTRL0_FSEL_100M 0x27 > > #define PHY_CTRL1 0x4 > #define PHY_CTRL1_RESET BIT(0) > @@ -108,6 +109,7 @@ struct tca_blk { > struct imx8mq_usb_phy { > struct phy *phy; > struct clk *clk; > + struct clk *alt_clk; > void __iomem *base; > struct regulator *vbus; > struct tca_blk *tca; > @@ -582,7 +584,8 @@ static int imx8mp_usb_phy_init(struct phy *phy) > /* USB3.0 PHY signal fsel for 24M ref */ > value = readl(imx_phy->base + PHY_CTRL0); > value &= ~PHY_CTRL0_FSEL_MASK; > - value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M); > + value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, imx_phy->alt_clk ? > + PHY_CTRL0_FSEL_100M : PHY_CTRL0_FSEL_24M); > writel(value, imx_phy->base + PHY_CTRL0); > > /* Disable alt_clk_en and use internal MPLL clocks */ > @@ -626,13 +629,24 @@ static int imx8mq_phy_power_on(struct phy *phy) > if (ret) > return ret; > > - return clk_prepare_enable(imx_phy->clk); > + ret = clk_prepare_enable(imx_phy->clk); > + if (ret) > + return ret; > + > + ret = clk_prepare_enable(imx_phy->alt_clk); > + if (ret) { > + clk_disable_unprepare(imx_phy->clk); > + return ret; > + } > + > + return ret; > } > > static int imx8mq_phy_power_off(struct phy *phy) > { > struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy); > > + clk_disable_unprepare(imx_phy->alt_clk); > clk_disable_unprepare(imx_phy->clk); > regulator_disable(imx_phy->vbus); > > @@ -681,6 +695,11 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev) > return PTR_ERR(imx_phy->clk); > } > > + imx_phy->alt_clk = devm_clk_get_optional(dev, "alt"); > + if (IS_ERR(imx_phy->alt_clk)) > + return dev_err_probe(dev, PTR_ERR(imx_phy->alt_clk), > + "Failed to get alt clk\n"); > + > imx_phy->base = devm_platform_ioremap_resource(pdev, 0); > if (IS_ERR(imx_phy->base)) > return PTR_ERR(imx_phy->base); > >