From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 328701F778A; Wed, 13 Nov 2024 09:20:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731489626; cv=none; b=Yyh3fgp51l/zUz1uFWAdsHSvmruXbsMtGjURmSmaLiThMUf3DnH5LNm3ZjEp8yupbCwHBiBxCbMdvRwx+YtCmyHDTkVrHc1FVG3vcuHqK4mOYwBX/aD9Ljtecvn0dbG+0CR7xEUdyj3FzN2JmbpWYvAGA9HBk+swBeavOwXKS2A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731489626; c=relaxed/simple; bh=O5B4rkqoM1HLtJD14rfhXRQ5yGxOyymMiwBeZ8fSqDE=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=p75Rce7U/BcUbRrdMs6L8Bx40OL32hoSMxuxxAgcHO+TPFPusqh1lTCsnWPyQWMK5ayWcaUkyhOwRYB4nRL9pxKnrCSAov/TV94i/qKGm4exIFC9+2324/F4v8m9y5J4wmmk0sRoXpup9RIwSZ0Z74VnvNtSDFY32PDGrJoX/Y8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=J248sb7c; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="J248sb7c" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AD70dmN019298; Wed, 13 Nov 2024 09:19:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= +jlEdp9U4UAYgw1Y7c/ImZvXJkE28m4D+/dF8fc7XOk=; b=J248sb7cFUl1nTDA sMFNX95fX4RZflfyRqUmFQEcVPvBHI+MFTWFvjkzinGzvEJ2ycnBKcmlXS5EosRj Niqh2WvFC93d00VJgozbYf+aZ0734bjyW3AqHFeNYIYVUoT7/N1S36aVxP7n51vI /ieeHdAawpNACvAQZkCFFW9OH4SixAwAY9d9jt3cWPJdCAvNNvGcvtur65UQ13Ys aQYpyVVDj3zQpSdSTvJKFWmWtNCtERmNRWvc8eIVifoEw1XVGAoTGcMmJIeD3W/S CtbYoEtICLlVZcUiKBw8hCjLGAoP7IwSUGys3/vIdlOj4CbGJS+MFuwW52O3URm/ Y/34Sg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42vqbm0bdd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 09:19:59 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AD9Jwvu004597 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 09:19:58 GMT Received: from [10.64.68.72] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 01:19:52 -0800 Message-ID: <28069114-9893-486b-a8d8-4c8b9ada1b0c@quicinc.com> Date: Wed, 13 Nov 2024 17:19:49 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/4] arm64: dts: qcom: qcs615: add UFS node To: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio CC: Vinod Koul , Kishon Vijay Abraham I , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross , , , , , , , , , References: <20241017042300.872963-1-quic_liuxin@quicinc.com> <20241017042300.872963-4-quic_liuxin@quicinc.com> <5fe37609-ed58-4617-bd5f-90edc90f5d8b@oss.qualcomm.com> From: Xin Liu In-Reply-To: <5fe37609-ed58-4617-bd5f-90edc90f5d8b@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bi-SqTW8PKTJtqASsU22B0m18Sor4LXa X-Proofpoint-GUID: bi-SqTW8PKTJtqASsU22B0m18Sor4LXa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 clxscore=1011 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130081 在 2024/10/26 3:24, Konrad Dybcio 写道: > On 17.10.2024 6:22 AM, Xin Liu wrote: >> From: Sayali Lokhande >> >> Add the UFS Host Controller node and its PHY for QCS615 SoC. >> >> Signed-off-by: Sayali Lokhande >> Co-developed-by: Xin Liu >> Signed-off-by: Xin Liu >> --- > > + Taniya (see below) > >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 74 ++++++++++++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index fcba83fca7cf..689418466dc2 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -458,6 +458,80 @@ mmss_noc: interconnect@1740000 { >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + ufs_mem_hc: ufs@1d84000 { > > ufshc@ would be consistent with other files in dts/qcom > I referred to qcom files such as sa8775p/sm8550/sm8650 etc.All use ufs@ > >> + compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> + reg = <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>; >> + reg-names = "std", "ice"; > > One per line, please Thank you, I will fix it next version. > >> + interrupts = ; >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + lanes-per-direction = <1>; >> + #reset-cells = <1>; >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x300 0x0>; >> + dma-coherent; >> + >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "ice_core_clk"; >> + freq-table-hz = <50000000 200000000>, >> + <0 0>, >> + <0 0>, >> + <37500000 150000000>, >> + <0 0>, >> + <0 0>, >> + <0 0>, >> + <75000000 300000000>; > > Please try to match the order of properties present in sm8650.dtsi Thank you, I will fix it next version. > > And please use an OPP table instead of freq-table-hz (see sm8*5*50.dtsi) Thank you, I will fix it next version. > >> + >> + status = "disabled"; >> + }; >> + >> + ufs_mem_phy: phy@1d87000 { >> + compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; >> + reg = <0x0 0x01d87000 0x0 0xe00>; > > This register region is a bit longer I just confirmed again, there's no problem here. > >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&gcc GCC_UFS_MEM_CLKREF_CLK>; >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + #clock-cells = <1>; > > The PHY is a clock provider. Normally, it's a parent of > gcc_ufs_phy_[rt]x_symbol_n clocks. > > Taniya, could you please wire that up in your patchset? > > Konrad