From: "NG, TZE YEE" <tze.yee.ng@altera.com>
To: "Kathpalia, Tanmay" <tanmay.kathpalia@altera.com>,
Adrian Hunter <adrian.hunter@intel.com>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/4] mmc: sdhci-cadence: add PHY settle after tuning for SD6HC
Date: Fri, 30 Oct 2026 15:50:41 +0800 [thread overview]
Message-ID: <28350860-199c-41af-a1df-54face030045@altera.com> (raw)
In-Reply-To: <f22270ec-a44b-4836-a0a1-5c7c3b10ce5f@altera.com>
On 30/10/2026 3:04 pm, Kathpalia, Tanmay wrote:
>
> On 30-10-2026 10:55, NG, TZE YEE wrote:
>> Hi Tanmay,
>>
>> Thanks for the detailed walk-through against the spec, it matches what
>> I see on the hardware.
>>
>>
>
> Hi Tze,
>
> Thanks for testing this, and I'm glad the abort approach worked on your
> board. The HS400 and SDR104 results, and the ftrace showing CMD12 after
> the failing CMD21, are exactly the confirmation I was looking for.
>
> I had already written this change while going through the tuning path,
> and I was planning to send it over the weekend once the remaining
> checks were done. Since you may already be folding the same fix into
> v3, how would you like to proceed? I'm happy to send the patch, or
> if you would rather carry it yourself, please add a Suggested-by tag.
>
> Regards,
> Tanmay
Hi Tanmay,
I'd like to carry it in my series. Patch 1 there currently adds the
unconditional PHY settle, so I'll replace that patch with the
abort-on-command-error change and credit you with:
Suggested-by: Tanmay Kathpalia tanmay.kathpalia@altera.com
It'll go in as patch 1 of v3. Once I've confirmed the ps-vs-count
question on cdns,ddr-read-dqs-delay with Krzysztof, I'll send out v3.
Thanks again,
Tze Yee
next prev parent reply other threads:[~2026-10-30 7:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 2:14 [PATCH v2 0/4] mmc: sdhci-cadence: SD6HC DDR50/DDR52 read-path tuning and fixes tze.yee.ng
2026-10-09 2:14 ` [PATCH v2 1/4] mmc: sdhci-cadence: add PHY settle after tuning for SD6HC tze.yee.ng
2026-10-25 20:17 ` Kathpalia, Tanmay
2026-10-30 5:25 ` NG, TZE YEE
2026-10-30 7:04 ` Kathpalia, Tanmay
2026-10-30 7:50 ` NG, TZE YEE [this message]
2026-10-09 2:14 ` [PATCH v2 2/4] mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR tze.yee.ng
2026-10-09 2:14 ` [PATCH v2 3/4] dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning tze.yee.ng
2026-10-12 8:48 ` Krzysztof Kozlowski
2026-10-29 6:21 ` NG, TZE YEE
2026-10-09 2:14 ` [PATCH v2 4/4] mmc: sdhci-cadence6: read SD6HC DDR50 tuning from device tree tze.yee.ng
2026-10-29 13:25 ` Adrian Hunter
2026-10-30 6:03 ` NG, TZE YEE
2026-10-18 21:19 ` [PATCH v2 0/4] mmc: sdhci-cadence: SD6HC DDR50/DDR52 read-path tuning and fixes Kathpalia, Tanmay
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