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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Lad Prabhakar , Romain Gantois , Heiner Kallweit , Coia Prant , Coia Prant Cc: Neil Armstrong , Russell King , Shawn Lin , David Heidelberg , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 05/10] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Sat, 01 Aug 2026 18:28:11 +0200 Message-ID: <2847036.GUH7pLUipS@diego> In-Reply-To: <20260801142244.679437-7-coiaprant@gmail.com> References: <20260801142244.679437-2-coiaprant@gmail.com> <20260801142244.679437-7-coiaprant@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Am Samstag, 1. August 2026, 16:22:29 Mitteleurop=C3=A4ische Sommerzeit schr= ieb Coia Prant: > The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides > the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII > interfaces via its four MII ports. Add the XPCS device node and > its pcs-mii sub-nodes to the SoC device tree. >=20 > The XPCS device is accessed via the APB3 bus at 0xfda00000 and > requires the CSR clock (PCLK_XPCS) for register access and the EEE > clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The > PD_PIPE power domain must be enabled before any register access. >=20 > Also add two fixed-clock nodes (xpcs_gmac0_clk and xpcs_gmac1_clk) > providing the 125 MHz reference clock for the GMACs when operating > with XPCS. These clocks are used as the assigned-clock-parents > for the respective GMAC nodes in board-level device trees. >=20 > The XPCS node and its pcs-mii sub-nodes are disabled by default and > must be enabled at the board level when 1000BASE-X/SGMII/QSGMII is > in use. The fixed-clock nodes are always present and do not have a > status property, as they are static clock sources. >=20 > The XPCS node also requires a reference to the appropriate Naneng > Combo PHY via the phys property at the board level. >=20 > Signed-off-by: Coia Prant > --- > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 45 ++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/d= ts/rockchip/rk3568.dtsi > index 3bc653f027f1f..989e164c0eb39 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -110,6 +110,51 @@ sata0: sata@fc000000 { > status =3D "disabled"; > }; > =20 > + xpcs: pcs@fda00000 { > + compatible =3D "rockchip,rk3568-xpcs"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + reg =3D <0x0 0xfda00000 0x0 0x200000>; > + clocks =3D <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; > + clock-names =3D "csr", "eee"; > + power-domains =3D <&power RK3568_PD_PIPE>; > + status =3D "disabled"; > + > + xpcs_mii0: pcs-mii@0 { > + reg =3D <0>; > + status =3D "disabled"; > + }; > + > + xpcs_mii1: pcs-mii@1 { > + reg =3D <1>; > + status =3D "disabled"; > + }; > + > + xpcs_mii2: pcs-mii@2 { > + reg =3D <2>; > + status =3D "disabled"; > + }; > + > + xpcs_mii3: pcs-mii@3 { > + reg =3D <3>; > + status =3D "disabled"; > + }; > + }; > + > + xpcs_gmac0_clk: xpcs-gmac0-clock { > + compatible =3D "fixed-clock"; > + clock-frequency =3D <125000000>; > + clock-output-names =3D "clk_gmac0_xpcs_mii"; > + #clock-cells =3D <0>; > + }; > + > + xpcs_gmac1_clk: xpcs-gmac1-clock { > + compatible =3D "fixed-clock"; > + clock-frequency =3D <125000000>; > + clock-output-names =3D "clk_gmac1_xpcs_mii"; > + #clock-cells =3D <0>; > + }; I don't fully believe those clocks are "just there" inside the SoC. Instead I _assume_ they are generated by some oscillator on the individual boards? Because as described there, they would be just magically be there. So please aim for a real clock description (likely on a board-level) Heiko