From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org,
kw@linux.com, krzysztof.kozlowski+dt@linaro.org,
vkoul@kernel.org
Cc: bhelgaas@google.com, kishon@kernel.org,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 08/13] ARM: dts: qcom: sdx55: List the property values vertically
Date: Mon, 27 Feb 2023 09:46:33 +0100 [thread overview]
Message-ID: <2852ca77-81fd-0e39-5030-d9d0f483ea0a@linaro.org> (raw)
In-Reply-To: <20230224105906.16540-9-manivannan.sadhasivam@linaro.org>
On 24.02.2023 11:59, Manivannan Sadhasivam wrote:
> To align with the rest of the devicetree files and the relative properties,
> let's list the values of properties such as {reg/clock/interrupt}-names
> vertically.
>
> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++-----
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index b411c4ae34c3..61fdd601fc26 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -393,7 +393,11 @@ pcie_ep: pcie-ep@1c00000 {
> <0x40001000 0x1000>,
> <0x40200000 0x100000>,
> <0x01c03000 0x3000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "addr_space",
> "mmio";
>
> qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> @@ -405,12 +409,18 @@ pcie_ep: pcie-ep@1c00000 {
> <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> <&gcc GCC_PCIE_SLEEP_CLK>,
> <&gcc GCC_PCIE_0_CLKREF_CLK>;
> - clock-names = "aux", "cfg", "bus_master", "bus_slave",
> - "slave_q2a", "sleep", "ref";
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep",
> + "ref";
>
> interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "global", "doorbell";
> + interrupt-names = "global",
> + "doorbell";
> reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> resets = <&gcc GCC_PCIE_BCR>;
> @@ -434,7 +444,10 @@ pcie_phy: phy@1c07000 {
> <&gcc GCC_PCIE_CFG_AHB_CLK>,
> <&gcc GCC_PCIE_0_CLKREF_CLK>,
> <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "refgen";
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "refgen";
>
> resets = <&gcc GCC_PCIE_PHY_BCR>;
> reset-names = "phy";
next prev parent reply other threads:[~2023-02-27 9:08 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 10:58 [PATCH v2 00/13] Add PCIe RC support to Qcom SDX55 SoC Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 01/13] dt-bindings: PCI: qcom: Update maintainers entry Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 02/13] dt-bindings: PCI: qcom: Add iommu properties Manivannan Sadhasivam
2023-02-27 19:55 ` Rob Herring
2023-02-28 8:20 ` Manivannan Sadhasivam
2023-03-01 14:58 ` Rob Herring
2023-03-08 8:00 ` Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 03/13] dt-bindings: PCI: qcom: Add SDX55 SoC Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Manivannan Sadhasivam
2023-02-24 10:58 ` [PATCH v2 06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} Manivannan Sadhasivam
2023-02-24 10:59 ` [PATCH v2 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Manivannan Sadhasivam
2023-02-27 8:46 ` Konrad Dybcio
2023-02-24 10:59 ` [PATCH v2 08/13] ARM: dts: qcom: sdx55: List the property values vertically Manivannan Sadhasivam
2023-02-27 8:46 ` Konrad Dybcio [this message]
2023-02-24 10:59 ` [PATCH v2 09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Manivannan Sadhasivam
2023-02-27 8:47 ` Konrad Dybcio
2023-02-24 10:59 ` [PATCH v2 10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down Manivannan Sadhasivam
2023-02-27 8:47 ` Konrad Dybcio
2023-02-24 10:59 ` [PATCH v2 11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Manivannan Sadhasivam
2023-02-24 10:59 ` [PATCH v2 12/13] phy: qcom-qmp-pcie: Add RC " Manivannan Sadhasivam
2023-02-24 10:59 ` [PATCH v2 13/13] PCI: qcom: Add support for SDX55 SoC Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2852ca77-81fd-0e39-5030-d9d0f483ea0a@linaro.org \
--to=konrad.dybcio@linaro.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=robh@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).