From: Arnd Bergmann <arnd@arndb.de>
To: Sricharan R <sricharan@codeaurora.org>
Cc: devicetree@vger.kernel.org, architt@codeaurora.org,
linux-arm-msm@vger.kernel.org, joro@8bytes.org,
iommu@lists.linux-foundation.org, robdclark@gmail.com,
srinivas.kandagatla@linaro.org,
laurent.pinchart@ideasonboard.com, treding@nvidia.com,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,
stepanm@codeaurora.org
Subject: Re: [PATCH V5 6/7] iommu/msm: Use writel_relaxed and add a barrier
Date: Fri, 20 May 2016 14:20:52 +0200 [thread overview]
Message-ID: <2864715.kytdDZX8IX@wuerfel> (raw)
In-Reply-To: <3164695.VzCnHHyi7r@wuerfel>
On Friday 20 May 2016 13:44:10 Arnd Bergmann wrote:
> > #define GET_CTX_REG(reg, base, ctx) \
> > (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
> >
> > -#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
> > +/*
> > + * The writes to the global/context registers needs to be synced only after
> > + * all the configuration writes are done. So use relaxed accessors and
> > + * a barrier at the end.
> > + */
> > +#define SET_GLOBAL_REG_RELAXED(reg, base, val) \
> > + writel_relaxed((val), ((base) + (reg)))
> >
> > -#define SET_CTX_REG(reg, base, ctx, val) \
> > - writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
> > +#define SET_CTX_REG_RELAXED(reg, base, ctx, val) \
> > + writel_relaxed((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
>
> Please add the relaxed accessors first in a separate patch, and then
> change over one user at a time before you remove the non-relaxed ones.
>
> It's hard to believe that all users are actually performance critical,
> so start with the ones that gain the most performance. As commented above,
> some of the conversions seem particularly fishy and it's likely that
> a slow reset() function should not be fixed by making reset() faster
> but by calling it less often.
One more thing, please also convert them into inline functions when you modify
them, and use normal names such as
static inline void msm_iommu_write(struct msm_iommu_dev *iommu, unsigned int reg, u32 val)
{
writel(val, iommu->base + reg);
}
static inline void msm_iommu_context_write(struct msm_iommu_ctx_dev *ctx, unsigned int reg, u32 val)
{
writel(val, ctx->iommu->base + ctx << CTX_SHIFT + reg, val);
}
Arnd
next prev parent reply other threads:[~2016-05-20 12:20 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-20 10:54 [PATCH V5 0/7] iommu/msm: Add DT adaptation and generic bindings support Sricharan R
2016-05-20 10:54 ` [PATCH V5 1/7] iommu/msm: Add DT adaptation Sricharan R
2016-05-20 10:54 ` [PATCH V5 2/7] documentation: iommu: Add bindings for msm,iommu-v0 ip Sricharan R
[not found] ` <1463741694-1735-3-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-05-23 21:23 ` Rob Herring
[not found] ` <1463741694-1735-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-05-20 10:54 ` [PATCH V5 3/7] iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c Sricharan R
2016-05-23 8:10 ` [PATCH V5 0/7] iommu/msm: Add DT adaptation and generic bindings support Srinivas Kandagatla
2016-05-20 10:54 ` [PATCH V5 4/7] iommu/msm: Add support for generic master bindings Sricharan R
2016-05-20 10:54 ` [PATCH V5 5/7] iommu/msm: use generic ARMV7S short descriptor pagetable ops Sricharan R
2016-05-20 10:54 ` [PATCH V5 6/7] iommu/msm: Use writel_relaxed and add a barrier Sricharan R
[not found] ` <1463741694-1735-7-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-05-20 11:44 ` Arnd Bergmann
2016-05-20 12:20 ` Arnd Bergmann [this message]
2016-05-23 6:05 ` Sricharan
2016-05-24 14:00 ` Arnd Bergmann
2016-05-25 10:45 ` Sricharan
2016-05-25 12:18 ` Arnd Bergmann
2016-05-25 13:19 ` Sricharan
2016-05-25 14:15 ` Arnd Bergmann
2016-05-25 16:49 ` Sricharan
2016-05-20 10:54 ` [PATCH V5 7/7] iommu/msm: Remove driver BROKEN Sricharan R
2016-05-23 2:53 ` [PATCH V5 0/7] iommu/msm: Add DT adaptation and generic bindings support Archit Taneja
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