[PATCH 0/6] arm64: dts: qcom: sm8750: Introduce crypto support for SM8750

[PATCH 0/6] arm64: dts: qcom: sm8750: Introduce crypto support for SM8750

[Melody Olvera]

Document and describe the crypto engines and random number generators
on the SM8750 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Gaurav Kashyap (6):
      dt-bindings: crypto: qcom-qce: Document the SM8750 crypto engine
      arm64: dts: qcom: sm8750: Add QCrypto nodes
      dt-bindings: crypto: qcom,prng: Document SM8750 RNG
      arm64: dts: qcom: sm8750: Add TRNG nodes
      dt-bindings: crypto: qcom,inline-crypto-engine: Document the SM8750 ICE
      arm64: dts: qcom: sm8750: Add ICE nodes

 .../bindings/crypto/qcom,inline-crypto-engine.yaml |  1 +
 .../devicetree/bindings/crypto/qcom,prng.yaml      |  1 +
 .../devicetree/bindings/crypto/qcom-qce.yaml       |  1 +
 arch/arm64/boot/dts/qcom/sm8750.dtsi               | 43 ++++++++++++++++++++++
 4 files changed, 46 insertions(+)
---
base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
change-id: 20250107-sm8750_crypto_master-12e2fc2fcf32

Best regards,
-- 
Melody Olvera <quic_molvera@quicinc.com>

[PATCH 1/6] dt-bindings: crypto: qcom-qce: Document the SM8750 crypto engine

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Document the crypto engine on the SM8750 Platform.

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 7f8c0d55f6f5c300c5c5cbfefee03af628d49d7a..3ed56d9d378e38a7ed3f5cd606c4dc20955194f0 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -54,6 +54,7 @@ properties:
               - qcom,sm8450-qce
               - qcom,sm8550-qce
               - qcom,sm8650-qce
+              - qcom,sm8750-qce
           - const: qcom,sm8150-qce
           - const: qcom,qce
 

-- 
2.46.1

[PATCH 2/6] arm64: dts: qcom: sm8750: Add QCrypto nodes

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c9cbd7067ae28cded 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 {
 			#interconnect-cells = <2>;
 		};
 
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x0 0x01dc4000 0x0 0x28000>;
+
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+			#dma-cells = <1>;
+
+			iommus = <&apps_smmu 0x480 0>,
+				 <&apps_smmu 0x481 0>;
+
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce";
+			reg = <0x0 0x01dfa000 0x0 0x6000>;
+
+			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "memory";
+
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+
+			iommus = <&apps_smmu 0x480 0>,
+				 <&apps_smmu 0x481 0>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x20000>;

-- 
2.46.1

[PATCH 3/6] dt-bindings: crypto: qcom,prng: Document SM8750 RNG

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Document SM8750 compatible for the True Random Number Generator.

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index d38e8d3b2f3a83dcb0e3559a7aaedb5d49df18f4..5e6f8b6425454d6440a8653567235380d934cc2c 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -27,6 +27,7 @@ properties:
               - qcom,sm8450-trng
               - qcom,sm8550-trng
               - qcom,sm8650-trng
+              - qcom,sm8750-trng
           - const: qcom,trng
 
   reg:

-- 
2.46.1

[PATCH 4/6] arm64: dts: qcom: sm8750: Add TRNG nodes

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Add the SM8750 nodes for the True Random Number Generator (TRNG).

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 1ddb33ea83885e73bf15244c9cbd7067ae28cded..9b2ac8c30013b02ca78140eb4144b4530aba5d6a 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -1883,6 +1883,11 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
 			};
 		};
 
+		rng: rng@10c3000 {
+			compatible = "qcom,sm8750-trng", "qcom,trng";
+			reg = <0x0 0x010c3000 0x0 0x1000>;
+		};
+
 		cnoc_main: interconnect@1500000 {
 			compatible = "qcom,sm8750-cnoc-main";
 			reg = <0x0 0x01500000 0x0 0x16080>;

-- 
2.46.1

[PATCH 5/6] dt-bindings: crypto: qcom,inline-crypto-engine: Document the SM8750 ICE

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Document the Inline Crypto Engine (ICE) on the SM8750 Platform.

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 657693867ddfc9dd3633b52633519ca101f59d7c..08fe6a707a3714ff11d01b36afc8a2aab1ad490c 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -20,6 +20,7 @@ properties:
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
+          - qcom,sm8750-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:

-- 
2.46.1

[PATCH 6/6] arm64: dts: qcom: sm8750: Add ICE nodes

[Melody Olvera]

From: Gaurav Kashyap <quic_gaurkash@quicinc.com>

Add the SM8750 nodes for the UFS Inline Crypto Engine (ICE).

Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 9b2ac8c30013b02ca78140eb4144b4530aba5d6a..63231f4d72e2ca2a109efff00ab7a21c7475888a 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -1944,6 +1944,14 @@ mmss_noc: interconnect@1780000 {
 			#interconnect-cells = <2>;
 		};
 
+		ice: crypto@1d88000 {
+			compatible = "qcom,sm8750-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
 		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x0 0x01dc4000 0x0 0x28000>;

-- 
2.46.1

Re: [PATCH 1/6] dt-bindings: crypto: qcom-qce: Document the SM8750 crypto engine

[Rob Herring (Arm)]

On Mon, 13 Jan 2025 13:16:21 -0800, Melody Olvera wrote:
> From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> 
> Document the crypto engine on the SM8750 Platform.
> 
> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 3/6] dt-bindings: crypto: qcom,prng: Document SM8750 RNG

[Rob Herring (Arm)]

On Mon, 13 Jan 2025 13:16:23 -0800, Melody Olvera wrote:
> From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> 
> Document SM8750 compatible for the True Random Number Generator.
> 
> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 5/6] dt-bindings: crypto: qcom,inline-crypto-engine: Document the SM8750 ICE

[Rob Herring (Arm)]

On Mon, 13 Jan 2025 13:16:25 -0800, Melody Olvera wrote:
> From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> 
> Document the Inline Crypto Engine (ICE) on the SM8750 Platform.
> 
> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/6] arm64: dts: qcom: sm8750: Add QCrypto nodes

[Stephan Gerhold]

On Mon, Jan 13, 2025 at 01:16:22PM -0800, Melody Olvera wrote:
> From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> 
> Add the QCE and Crypto BAM DMA nodes.
> 
> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c9cbd7067ae28cded 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 {
>  			#interconnect-cells = <2>;
>  		};
>  
> +		cryptobam: dma-controller@1dc4000 {
> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg = <0x0 0x01dc4000 0x0 0x28000>;
> +
> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			#dma-cells = <1>;
> +
> +			iommus = <&apps_smmu 0x480 0>,
> +				 <&apps_smmu 0x481 0>;

Should be equivalent to iommus = <&apps_smmu 0x480 0x1>?

> +
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;

If you don't have clocks here, you need to provide num-channels and
qcom,num-ees. Otherwise, there is a risk this will crash if the BAM is
not up while being probed.

Thanks,
Stephan

Re: [PATCH 0/6] arm64: dts: qcom: sm8750: Introduce crypto support for SM8750

[Herbert Xu]

On Mon, Jan 13, 2025 at 01:16:20PM -0800, Melody Olvera wrote:
> Document and describe the crypto engines and random number generators
> on the SM8750 SoC.
> 
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Gaurav Kashyap (6):
>       dt-bindings: crypto: qcom-qce: Document the SM8750 crypto engine
>       arm64: dts: qcom: sm8750: Add QCrypto nodes
>       dt-bindings: crypto: qcom,prng: Document SM8750 RNG
>       arm64: dts: qcom: sm8750: Add TRNG nodes
>       dt-bindings: crypto: qcom,inline-crypto-engine: Document the SM8750 ICE
>       arm64: dts: qcom: sm8750: Add ICE nodes
> 
>  .../bindings/crypto/qcom,inline-crypto-engine.yaml |  1 +
>  .../devicetree/bindings/crypto/qcom,prng.yaml      |  1 +
>  .../devicetree/bindings/crypto/qcom-qce.yaml       |  1 +
>  arch/arm64/boot/dts/qcom/sm8750.dtsi               | 43 ++++++++++++++++++++++
>  4 files changed, 46 insertions(+)
> ---
> base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
> change-id: 20250107-sm8750_crypto_master-12e2fc2fcf32
> 
> Best regards,
> -- 
> Melody Olvera <quic_molvera@quicinc.com>

Patches 1/3/5 applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH 6/6] arm64: dts: qcom: sm8750: Add ICE nodes

[Konrad Dybcio]

On 13.01.2025 10:16 PM, Melody Olvera wrote:
> From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> 
> Add the SM8750 nodes for the UFS Inline Crypto Engine (ICE).
> 
> Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

RE: [PATCH 2/6] arm64: dts: qcom: sm8750: Add QCrypto nodes

[Gaurav Kashyap (QUIC)]

On Thu, Jan 16, 2025 at 9:06 AM PST, Stephan Gerhold wrote:
> On Mon, Jan 13, 2025 at 01:16:22PM -0800, Melody Olvera wrote:
> > From: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> >
> > Add the QCE and Crypto BAM DMA nodes.
> >
> > Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
> > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/sm8750.dtsi | 30
> > ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > index
> >
> 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..1ddb33ea83885e73bf15244c
> 9cbd
> > 7067ae28cded 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> > @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 {
> >                       #interconnect-cells = <2>;
> >               };
> >
> > +             cryptobam: dma-controller@1dc4000 {
> > +                     compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> > +                     reg = <0x0 0x01dc4000 0x0 0x28000>;
> > +
> > +                     interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                     #dma-cells = <1>;
> > +
> > +                     iommus = <&apps_smmu 0x480 0>,
> > +                              <&apps_smmu 0x481 0>;
> 
> Should be equivalent to iommus = <&apps_smmu 0x480 0x1>?
> 

Hello Stephan, we tried this out internally, and the use case was not functional.
The masks are explicitly mentioned in our hardware documents and we are just following that.

So, we are looking to keep it the same.

> > +
> > +                     qcom,ee = <0>;
> > +                     qcom,controlled-remotely;
> 
> If you don't have clocks here, you need to provide num-channels and
> qcom,num-ees. Otherwise, there is a risk this will crash if the BAM is not up
> while being probed.
> 

Ack.

> Thanks,
> Stephan

Regards,
Gaurav

Re: (subset) [PATCH 0/6] arm64: dts: qcom: sm8750: Introduce crypto support for SM8750

[Bjorn Andersson]

On Mon, 13 Jan 2025 13:16:20 -0800, Melody Olvera wrote:
> Document and describe the crypto engines and random number generators
> on the SM8750 SoC.
> 
> 

Applied, thanks!

[2/6] arm64: dts: qcom: sm8750: Add QCrypto nodes
      commit: eeb0f3e4ea67cb1c2dd7cacfef218bfa0ae56970
[4/6] arm64: dts: qcom: sm8750: Add TRNG nodes
      commit: 9f9dcac2f85e6a0641a4a4f7f3b2c35a984ed4cc
[6/6] arm64: dts: qcom: sm8750: Add ICE nodes
      commit: b1dac789c650a20a54d5089b23fbb800fb289b8b

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>