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Fri, 15 Nov 2024 04:59:25 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AF4xPAX004511 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 04:59:25 GMT Received: from [10.233.17.145] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 20:59:15 -0800 Message-ID: <288be342-952b-4210-afe7-6e194dfd54a9@quicinc.com> Date: Fri, 15 Nov 2024 12:59:12 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 To: Konrad Dybcio , Dmitry Baryshkov , Ziyue Zhang CC: , , , , , , , , , , , , , , , , , , , , References: <20241114095409.2682558-1-quic_ziyuzhan@quicinc.com> <20241114095409.2682558-5-quic_ziyuzhan@quicinc.com> <26943ea3-109c-473d-818b-2a08dba859ab@oss.qualcomm.com> From: Tingwei Zhang In-Reply-To: <26943ea3-109c-473d-818b-2a08dba859ab@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gW9MRU-f88Y10pYvrMlMAq6Z4DCIw1DZ X-Proofpoint-ORIG-GUID: gW9MRU-f88Y10pYvrMlMAq6Z4DCIw1DZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 bulkscore=0 mlxlogscore=691 lowpriorityscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 clxscore=1011 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150040 On 11/14/2024 9:03 PM, Konrad Dybcio wrote: > On 14.11.2024 1:10 PM, Dmitry Baryshkov wrote: >> On Thu, Nov 14, 2024 at 05:54:08PM +0800, Ziyue Zhang wrote: >>> Add configurations in devicetree for PCIe0, including registers, clocks, >>> interrupts and phy setting sequence. >>> >>> Signed-off-by: Ziyue Zhang >>> --- >>> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++- >>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++ >>> 2 files changed, 219 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >>> index 7eed19a694c3..9d7c8555ed38 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >>> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts >>> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 { >>> &gcc { >> >> The patch doesn't seem to update the gcc node in qcs8300.dtsi. Is there >> any reason to have the clocks property in the board data file? > > Definitely not. Ziyue, please move that change to the soc dtsi Gcc node is updated in board device tree due to sleep_clk is defined in board device tree. Sleep_clk is from PMIC instead SoC so we were requested to move sleep_clk to board device tree in previous review [1]. [1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/ > > Konrad -- Thanks, Tingwei