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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id n13-20020a170906724d00b006cedd6d7e24sm1545928ejk.119.2022.04.23.03.27.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 23 Apr 2022 03:27:40 -0700 (PDT) Message-ID: <288f55f3-b3ed-32b8-9a44-652f3d53617d@linaro.org> Date: Sat, 23 Apr 2022 12:27:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH V3 11/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192-sys-clock Content-Language: en-US To: Rex-BC Chen , mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com, chun-jie.chen@mediatek.com, wenst@chromium.org, runyang.chen@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> <20220422060152.13534-12-rex-bc.chen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220422060152.13534-12-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22/04/2022 08:01, Rex-BC Chen wrote: > We will use the infra_ao reset which is defined in mt8192-sys-clock. > The maximum value of reset-cells is 2. Therefore, we add this patch to > define it. Remove entire last sentence, does not make sense in the commit. > > Signed-off-by: Rex-BC Chen > --- > .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml > index 5705bcf1fe47..28ebcecc8258 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml > @@ -29,6 +29,9 @@ properties: > '#clock-cells': > const: 1 > > + '#reset-cells': > + maximum: 2 Why this is a maximum? Usually this is const, so how do you use it (with what values)? > + > required: > - compatible > - reg Best regards, Krzysztof