From: "David Lanzendörfer" <david.lanzendoerfer@o2s.ch>
To: "Emilio López" <emilio@elopez.com.ar>
Cc: Mike Turquette <mturquette@linaro.org>,
zhangfei <zhangfei.gao@linaro.org>, Arnd Bergmann <arnd@arndb.de>,
dinguyen@altera.com, mark.rutland@arm.com,
devicetree@vger.kernel.org, dinh.linux@gmail.com,
heiko@sntech.de, pawel.moll@arm.com, bzhao@marvell.com,
tgih.jun@samsung.com,
Peter De Schrijver <pdeschrijver@nvidia.com>,
linux-mmc@vger.kernel.org, dianders@chromium.org,
rob.herring@calxeda.com, jh80.chung@samsung.com,
alim.akhtar@samsung.com, cjb@laptop.org,
linux-arm-kernel@lists.infradead.org, ian.campbell@citrix.com,
Hans de Goede <hdegoede@redhat.com>, Chen-Yu Tsai <wens@csie.org>
Subject: Re: [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver
Date: Mon, 16 Dec 2013 22:54:21 +0100 [thread overview]
Message-ID: <2899559.jbTzDM2qtE@dizzy-6.site> (raw)
In-Reply-To: <52AF68DB.7090105@elopez.com.ar>
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Hi
> that takes the MMC clock (and only the MMC clock) and does the setup
> (it's basically configuring two values, "sample" and "output", into the
> clock register). I really don't know what does this do/why is it
> required/when is it used; I'm cc'ing Hans and David who can hopefully
> explain that part.
Since the read/write operations have to happen asynchronously and in a manner
so that the data provided by the SD-Card can be fetched on time, a specific
clock phase shift is required as you can see in the linked picture[1].
That's what the function is doing: It accesses the special registers of the
MMC clock device and configures this phase offset.
> I also saw a similar requirement from the gmac people (on cc too), who
> needed to set the phy type (or something like that) on one of the clock
> registers; so I'm thinking maybe a generic "tune something" approach
> that lets users configure some clock-dependent, arbitrary aspect of the
> clock is the way forward. Otherwise, we're going to end up bloating the
> clock framework with a lot of callback pointers that are going to be
> used in one or two clocks out of potentially hundreds on the whole system.
It totally makes sense, since GMAC will be doing asynchrous
operations as well.
-David
[1] http://www.chipestimate.com/techtalk/images/11022010_fig2_3.JPG
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next prev parent reply other threads:[~2013-12-16 21:54 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-12 20:30 [PATCHv6 0/5] socfpga: Enable SD/MMC support dinguyen
2013-12-12 20:30 ` [PATCHv6 1/5] mmc: dw_mmc: Add support to set the SDR and DDR timing through clock framework dinguyen
2013-12-15 2:05 ` zhangfei
2013-12-15 3:16 ` Dinh Nguyen
2013-12-15 4:37 ` zhangfei
[not found] ` <52AD320A.4030502-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2013-12-16 3:24 ` Dinh Nguyen
2013-12-16 3:38 ` Zhangfei Gao
2013-12-16 4:20 ` Seungwon Jeon
[not found] ` <1386880245-10192-1-git-send-email-dinguyen-EIB2kfCEclfQT0dZR+AlfA@public.gmane.org>
2013-12-12 20:30 ` [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver dinguyen-EIB2kfCEclfQT0dZR+AlfA
2013-12-14 21:33 ` Arnd Bergmann
2013-12-15 2:18 ` zhangfei
2013-12-15 4:51 ` Mike Turquette
2013-12-16 20:55 ` Emilio López
2013-12-16 21:06 ` Hans de Goede
2013-12-16 21:54 ` David Lanzendörfer [this message]
2013-12-18 20:10 ` Mike Turquette
2013-12-17 2:17 ` Chen-Yu Tsai
2013-12-12 20:30 ` [PATCHv6 3/5] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform dinguyen
2013-12-12 20:30 ` [PATCHv6 4/5] mmc: dw_mmc-socfpga: Remove the SOCFPGA specific platform for dw_mmc dinguyen
2013-12-12 20:30 ` [PATCHv6 5/5] ARM: socfpga_defconfig: enable SD/MMC support dinguyen
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