Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

[Michal Simek <michal.simek@amd.com>]

On 8/18/26 09:03, Krzysztof Kozlowski wrote:
> On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
>> From: Anirudha Sarangi <anirudha.sarangi@amd.com>
>>
>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
>> (Control and Status Register) interrupt controller.
>>
>> The SMMU CSR block acts as a vendor-specific interrupt controller
>> in front of the ARM SMMUv3, providing registers to enable and clear
>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
>> Interrupts must be acknowledged in this block before being forwarded
>> to the parent interrupt controller (e.g. GIC).
>>
>> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
>> Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
>> ---
> 
> b4 got only this one patch, where is the rest?
> 
> Can finally people in AMD start using b4 to send patches? How many times
> I need to ask for that?

Not sure what you want me to say about it. I don't think that this is related to 
AMD but only individual developers.

There are also other tools for doing it not just b4. Everybody got these 
instructions but it is up to everybody to follow them. When something is sent 
out I can't do anything with it. (And internally this was sent as threaded 
multiple times).

Thanks,
Michal