* Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 [not found] ` <20210805205226.24880-3-jason-jh.lin@mediatek.com> @ 2021-08-06 11:28 ` Matthias Brugger 0 siblings, 0 replies; 2+ messages in thread From: Matthias Brugger @ 2021-08-06 11:28 UTC (permalink / raw) To: jason-jh.lin, Rob Herring, Chun-Kuang Hu, Philipp Zabel, Enric Balletbo i Serra, fshao Cc: David Airlie, Daniel Vetter, Fabien Parent, hsinyi, Yongqiang Niu, nancy.lin, singo.chang, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel Hi Jason, On 05/08/2021 22:52, jason-jh.lin wrote: > Add mt8195 vdosys0 clock driver name and routing table to > the driver data of mtk-mmsys. > I'd like to see the implementation of vdosys1 as well, to better understand why we need two compatibles. > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch is base on [1] > > [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding > https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/ Please add the binding description to this series. > --- > drivers/soc/mediatek/mt8195-mmsys.h | 96 ++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > include/linux/soc/mediatek/mtk-mmsys.h | 9 +++ > 3 files changed, 116 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h > new file mode 100644 > index 000000000000..9339a786ec5d > --- /dev/null > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H > +#define __SOC_MEDIATEK_MT8195_MMSYS_H > + > +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) > + > +#define MT8195_VDO0_SEL_IN 0xf34 > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22) > + > +#define MT8195_VDO0_SEL_OUT 0xf38 > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) > + > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 Please update the struct to the new version that includes a mask field. Regards, Matthias ^ permalink raw reply [flat|nested] 2+ messages in thread
[parent not found: <20210805205226.24880-8-jason-jh.lin@mediatek.com>]
* Re: [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 [not found] ` <20210805205226.24880-8-jason-jh.lin@mediatek.com> @ 2021-08-06 16:57 ` Chun-Kuang Hu 0 siblings, 0 replies; 2+ messages in thread From: Chun-Kuang Hu @ 2021-08-06 16:57 UTC (permalink / raw) To: jason-jh.lin Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, Enric Balletbo i Serra, fshao, David Airlie, Daniel Vetter, Fabien Parent, Hsin-Yi Wang, Yongqiang Niu, Nancy Lin, singo.chang, DTML, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, DRI Development Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道： > > Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver. > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > This patch is base on [1] > > [1] dt-bindings: mediatek: display: add mt8195 SoC binding > https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/ > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaadfea8c..00e9827acefe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > .fifo_size = 5 * SZ_1K, > }; > > +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { > + .fifo_size = 1920, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > .data = &mt8173_rdma_driver_data}, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = &mt8183_rdma_driver_data}, > + { .compatible = "mediatek,mt8195-disp-rdma", > + .data = &mt8195_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 5eb9c0a04447..9aebf73144c6 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSC0, > + DDP_COMPONENT_MERGE0, > + DDP_COMPONENT_DP_INTF0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { > + .main_path = mt8195_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8183-disp-dither", > .data = (void *)MTK_DISP_DITHER }, > + { .compatible = "mediatek,mt8195-disp-dsc", > + .data = (void *)MTK_DISP_DSC }, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > { .compatible = "mediatek,mt8183-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8195-disp-merge", > + .data = (void *)MTK_DISP_MERGE }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8195-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-od", > .data = (void *)MTK_DISP_OD }, > { .compatible = "mediatek,mt2701-disp-ovl", > @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8195-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt8173-disp-wdma", > @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + {.compatible = "mediatek,mt8195-vdosys0", > + .data = &mt8195_vdosys0_driver_data}, > { } > }; > MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); > -- > 2.18.0 > ^ permalink raw reply [flat|nested] 2+ messages in thread
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[not found] <20210805205226.24880-1-jason-jh.lin@mediatek.com>
[not found] ` <20210805205226.24880-3-jason-jh.lin@mediatek.com>
2021-08-06 11:28 ` [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Matthias Brugger
[not found] ` <20210805205226.24880-8-jason-jh.lin@mediatek.com>
2021-08-06 16:57 ` [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 Chun-Kuang Hu
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