* [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-03 22:39 ` Andi Shyti
2025-01-02 16:32 ` [PATCH v3 2/6] dt-bindings: clock: move qcom,x1e80100-camcc to its own file Bryan O'Donoghue
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Krzysztof Kozlowski
Add the x1e80100 CCI device string compatible.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index ef26ba6eda28e95875853fe5043fe11deb5af088..73144473b9b24e574bfc6bd7d8908f2f3895e087 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -34,6 +34,7 @@ properties:
- qcom,sm8450-cci
- qcom,sm8550-cci
- qcom,sm8650-cci
+ - qcom,x1e80100-cci
- const: qcom,msm8996-cci # CCI v2
"#address-cells":
@@ -224,6 +225,7 @@ allOf:
enum:
- qcom,sm8550-cci
- qcom,sm8650-cci
+ - qcom,x1e80100-cci
then:
properties:
clocks:
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible
2025-01-02 16:32 ` [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible Bryan O'Donoghue
@ 2025-01-03 22:39 ` Andi Shyti
0 siblings, 0 replies; 13+ messages in thread
From: Andi Shyti @ 2025-01-03 22:39 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Loic Poulain, Robert Foss, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Todor Tomov, Mauro Carvalho Chehab, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Vladimir Zapolskiy,
Jagadeesh Kona, Konrad Dybcio, linux-i2c, linux-arm-msm,
devicetree, linux-kernel, linux-media, linux-clk,
Krzysztof Kozlowski
Hi Bryan,
On Thu, Jan 02, 2025 at 04:32:06PM +0000, Bryan O'Donoghue wrote:
> Add the x1e80100 CCI device string compatible.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
this patch 1/6 has already been merged in i2c/i2c-host. You
should not send it anymore.
The rest of the patches are handled elsewere.
Thanks,
Andi
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 2/6] dt-bindings: clock: move qcom,x1e80100-camcc to its own file
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-01-02 16:32 ` [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-02 16:32 ` [PATCH v3 3/6] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Krzysztof Kozlowski
Add an x1e80100 camcc binding. x1e80100 has two power-domain parents unlike
other similar camcc controllers.
Differentiate the new structure into a unique camcc definition. Other
similar camcc controller setups can then be easily added to this one.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/clock/qcom,sm8450-camcc.yaml | 2 -
.../bindings/clock/qcom,x1e80100-camcc.yaml | 74 ++++++++++++++++++++++
2 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index 0766f66c7dc4f6b81afa01f156c490f4f742fcee..b88b6c9b399a4f8f3c67dd03e6cfc306963b868f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -19,7 +19,6 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
- include/dt-bindings/clock/qcom,x1e80100-camcc.h
properties:
compatible:
@@ -29,7 +28,6 @@ properties:
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- - qcom,x1e80100-camcc
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5bbbaa15a26090186e4ee4397ecba2f3c2541672
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on x1e80100
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ Qualcomm camera clock control module provides the clocks, resets and power
+ domains on x1e80100.
+
+ See also:
+ include/dt-bindings/clock/qcom,x1e80100-camcc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,x1e80100-camcc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Camera AHB clock from GCC
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source
+
+ power-domains:
+ items:
+ - description: A phandle to the MXC power-domain
+ - description: A phandle to the MMCX power-domain
+
+ required-opps:
+ maxItems: 1
+ description:
+ A phandle to an OPP node describing MMCX performance points.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+ - required-opps
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@ade0000 {
+ compatible = "qcom,x1e80100-camcc";
+ reg = <0xade0000 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 3/6] dt-bindings: media: Add qcom,x1e80100-camss
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-01-02 16:32 ` [PATCH v3 1/6] dt-bindings: i2c: qcom-cci: Document x1e80100 compatible Bryan O'Donoghue
2025-01-02 16:32 ` [PATCH v3 2/6] dt-bindings: clock: move qcom,x1e80100-camcc to its own file Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-02 16:32 ` [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Krzysztof Kozlowski
Add bindings for qcom,x1e80100-camss in order to support the camera
subsystem for x1e80100 as found in various Co-Pilot laptops.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..88eeac262f0e2974d1df43e0df7513fffbebd05c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
@@ -0,0 +1,367 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,x1e80100-camss
+
+ reg:
+ maxItems: 17
+
+ reg-names:
+ items:
+ - const: csid_wrapper
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy4
+ - const: csitpg0
+ - const: csitpg1
+ - const: csitpg2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe0
+ - const: vfe1
+
+ clocks:
+ maxItems: 29
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: camnoc_nrt_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe_lite
+ - const: cphy_rx_clk_src
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 13
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: cam_ahb
+ - const: cam_hf_mnoc
+ - const: cam_sf_mnoc
+ - const: cam_sf_icp_mnoc
+
+ iommus:
+ maxItems: 8
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+
+ vdd-csiphy-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to a PHY.
+
+ vdd-csiphy-1p2-supply:
+ description:
+ Phandle to 1.8V regulator supply to a PHY.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - vdd-csiphy-0p8-supply
+ - vdd-csiphy-1p2-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@acb6000 {
+ compatible = "qcom,x1e80100-camss";
+
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0ace4000 0 0x1000>,
+ <0 0x0ace6000 0 0x1000>,
+ <0 0x0ace8000 0 0x1000>,
+ <0 0x0acec000 0 0x4000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0ac71000 0 0x4000>;
+
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+
+ clock-names = "camnoc_rt_axi",
+ "camnoc_nrt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1800 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x1980 0x20>,
+ <&apps_smmu 0x1900 0x00>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>;
+ vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csiphy_ep0: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (2 preceding siblings ...)
2025-01-02 16:32 ` [PATCH v3 3/6] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-02 17:49 ` Vladimir Zapolskiy
2025-01-03 12:33 ` Konrad Dybcio
2025-01-02 16:32 ` [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
` (2 subsequent siblings)
6 siblings, 2 replies; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
of previous CAMCC blocks with the exception of having two required
power-domains not just one.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5c7b0c048d41a4ba3d74bbf77216ad09b652ed30 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
@@ -4647,6 +4648,21 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,x1e80100-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,x1e80100-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-01-02 16:32 ` [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
@ 2025-01-02 17:49 ` Vladimir Zapolskiy
2025-01-03 12:33 ` Konrad Dybcio
1 sibling, 0 replies; 13+ messages in thread
From: Vladimir Zapolskiy @ 2025-01-02 17:49 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk
Hi Bryan.
On 1/2/25 18:32, Bryan O'Donoghue wrote:
> Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
> of previous CAMCC blocks with the exception of having two required
> power-domains not just one.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5c7b0c048d41a4ba3d74bbf77216ad09b652ed30 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
> +#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
> @@ -4647,6 +4648,21 @@ usb_1_ss1_dwc3_ss: endpoint {
> };
> };
>
> + camcc: clock-controller@ade0000 {
> + compatible = "qcom,x1e80100-camcc";
> + reg = <0 0x0ade0000 0 0x20000>;
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&bi_tcxo_div2>,
> + <&bi_tcxo_ao_div2>,
> + <&sleep_clk>;
> + power-domains = <&rpmhpd RPMHPD_MXC>,
> + <&rpmhpd RPMHPD_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> mdss: display-subsystem@ae00000 {
> compatible = "qcom,x1e80100-mdss";
> reg = <0 0x0ae00000 0 0x1000>;
>
Looks good, thank you.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-01-02 16:32 ` [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
2025-01-02 17:49 ` Vladimir Zapolskiy
@ 2025-01-03 12:33 ` Konrad Dybcio
1 sibling, 0 replies; 13+ messages in thread
From: Konrad Dybcio @ 2025-01-03 12:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk
On 2.01.2025 5:32 PM, Bryan O'Donoghue wrote:
> Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
> of previous CAMCC blocks with the exception of having two required
> power-domains not just one.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (3 preceding siblings ...)
2025-01-02 16:32 ` [PATCH v3 4/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-02 17:57 ` Vladimir Zapolskiy
2025-01-02 16:32 ` [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
2025-01-08 4:43 ` (subset) [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bjorn Andersson
6 siblings, 1 reply; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Konrad Dybcio
Add in 2 CCI busses. One bus has two CCI bus master pinouts:
cci_i2c_scl0 = gpio101
cci_i2c_sda0 = gpio102
cci_i2c_scl1 = gpio103
cci_i2c_sda1 = gpio104
A second bus has a single CCI bus master pinout:
cci_i2c_scl2 = gpio105
cci_i2c_sda2 = gpio106
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722ca8afd49cd3c24 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
+
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac16000 0 0x1000>;
+
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0 0x0ade0000 0 0x20000>;
@@ -5271,6 +5349,78 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 239>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions
2025-01-02 16:32 ` [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
@ 2025-01-02 17:57 ` Vladimir Zapolskiy
0 siblings, 0 replies; 13+ messages in thread
From: Vladimir Zapolskiy @ 2025-01-02 17:57 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Konrad Dybcio
Hi Bryan.
On 1/2/25 18:32, Bryan O'Donoghue wrote:
> Add in 2 CCI busses. One bus has two CCI bus master pinouts:
> cci_i2c_scl0 = gpio101
> cci_i2c_sda0 = gpio102
> cci_i2c_scl1 = gpio103
> cci_i2c_sda1 = gpio104
>
> A second bus has a single CCI bus master pinout:
> cci_i2c_scl2 = gpio105
> cci_i2c_sda2 = gpio106
I notice that the change assigns "aon_cci" function to gpio235 and gpio236
pins, and they do serve as cci1_i2c1 sda/scl pins, thus here is the second
CCI bus master.
So, I assume the commit message is not correct...
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 5c7b0c048d41a4ba3d74bbf77216ad09b652ed30..97ebf5596dfc3caa920ef85722ca8afd49cd3c24 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -4648,6 +4648,84 @@ usb_1_ss1_dwc3_ss: endpoint {
> };
> };
>
> + cci0: cci@ac15000 {
> + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac15000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci0_default>;
> + pinctrl-1 = <&cci0_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@ac16000 {
> + compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac16000 0 0x1000>;
> +
> + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci1_default>;
> + pinctrl-1 = <&cci1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camcc: clock-controller@ade0000 {
> compatible = "qcom,x1e80100-camcc";
> reg = <0 0x0ade0000 0 0x20000>;
> @@ -5271,6 +5349,78 @@ tlmm: pinctrl@f100000 {
> gpio-ranges = <&tlmm 0 0 239>;
> wakeup-parent = <&pdc>;
>
> + cci0_default: cci0-default-state {
> + cci0_i2c0_default: cci0-i2c0-default-pins {
> + /* cci_i2c_sda0, cci_i2c_scl0 */
> + pins = "gpio101", "gpio102";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci0_i2c1_default: cci0-i2c1-default-pins {
> + /* cci_i2c_sda1, cci_i2c_scl1 */
> + pins = "gpio103", "gpio104";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_sleep: cci0-sleep-state {
> + cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
> + /* cci_i2c_sda0, cci_i2c_scl0 */
> + pins = "gpio101", "gpio102";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
> + /* cci_i2c_sda1, cci_i2c_scl1 */
> + pins = "gpio103", "gpio104";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_default: cci1-default-state {
> + cci1_i2c0_default: cci1-i2c0-default-pins {
> + /* cci_i2c_sda2, cci_i2c_scl2 */
> + pins = "gpio105","gpio106";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci1_i2c1_default: cci1-i2c1-default-pins {
> + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
> + pins = "gpio235","gpio236";
> + function = "aon_cci";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_sleep: cci1-sleep-state {
> + cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
> + /* cci_i2c_sda2, cci_i2c_scl2 */
> + pins = "gpio105","gpio106";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
> + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
> + pins = "gpio235","gpio236";
> + function = "aon_cci";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> qup_i2c0_data_clk: qup-i2c0-data-clk-state {
> /* SDA, SCL */
> pins = "gpio0", "gpio1";
>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (4 preceding siblings ...)
2025-01-02 16:32 ` [PATCH v3 5/6] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
@ 2025-01-02 16:32 ` Bryan O'Donoghue
2025-01-02 18:51 ` Vladimir Zapolskiy
2025-01-08 4:43 ` (subset) [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bjorn Andersson
6 siblings, 1 reply; 13+ messages in thread
From: Bryan O'Donoghue @ 2025-01-02 16:32 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Konrad Dybcio
Add dtsi to describe the xe180100 CAMSS block
4 x CSIPHY
2 x CSID
2 x CSID Lite
2 x IFE
2 x IFE Lite
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 97ebf5596dfc3caa920ef85722ca8afd49cd3c24..0b5b48d2c59e0b18816ea131e0f687b8bf84e1da 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4726,6 +4726,191 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ camss: isp@acb6000 {
+ compatible = "qcom,x1e80100-camss";
+
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0ace4000 0 0x2000>,
+ <0 0x0ace6000 0 0x2000>,
+ <0 0x0ace8000 0 0x2000>,
+ <0 0x0acec000 0 0x2000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0ac71000 0 0x4000>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "camnoc_nrt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1800 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x1900 0x00>,
+ <&apps_smmu 0x1980 0x20>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0 0x0ade0000 0 0x20000>;
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition
2025-01-02 16:32 ` [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
@ 2025-01-02 18:51 ` Vladimir Zapolskiy
0 siblings, 0 replies; 13+ messages in thread
From: Vladimir Zapolskiy @ 2025-01-02 18:51 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Konrad Dybcio
On 1/2/25 18:32, Bryan O'Donoghue wrote:
> Add dtsi to describe the xe180100 CAMSS block
>
> 4 x CSIPHY
> 2 x CSID
> 2 x CSID Lite
> 2 x IFE
> 2 x IFE Lite
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++
> 1 file changed, 185 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 97ebf5596dfc3caa920ef85722ca8afd49cd3c24..0b5b48d2c59e0b18816ea131e0f687b8bf84e1da 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -4726,6 +4726,191 @@ cci1_i2c1: i2c-bus@1 {
> };
> };
>
> + camss: isp@acb6000 {
> + compatible = "qcom,x1e80100-camss";
> +
> + reg = <0 0x0acb6000 0 0x1000>,
> + <0 0x0acb7000 0 0x2000>,
> + <0 0x0acb9000 0 0x2000>,
> + <0 0x0acbb000 0 0x2000>,
> + <0 0x0acc6000 0 0x1000>,
> + <0 0x0acca000 0 0x1000>,
> + <0 0x0ace4000 0 0x2000>,
> + <0 0x0ace6000 0 0x2000>,
> + <0 0x0ace8000 0 0x2000>,
> + <0 0x0acec000 0 0x2000>,
> + <0 0x0acf6000 0 0x1000>,
> + <0 0x0acf7000 0 0x1000>,
> + <0 0x0acf8000 0 0x1000>,
> + <0 0x0acc7000 0 0x2000>,
> + <0 0x0accb000 0 0x2000>,
> + <0 0x0ac62000 0 0x4000>,
> + <0 0x0ac71000 0 0x4000>;
> + reg-names = "csid_wrapper",
> + "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy4",
> + "csitpg0",
> + "csitpg1",
> + "csitpg2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe0",
> + "vfe1";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
> + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
> + <&camcc CAM_CC_CORE_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_rt_axi",
> + "camnoc_nrt_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "cpas_fast_ahb",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "cpas_vfe_lite",
> + "cphy_rx_clk_src",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "cam_ahb",
> + "cam_hf_mnoc",
> + "cam_sf_mnoc",
> + "cam_sf_icp_mnoc";
> +
> + iommus = <&apps_smmu 0x800 0x60>,
> + <&apps_smmu 0x860 0x60>,
> + <&apps_smmu 0x1800 0x60>,
> + <&apps_smmu 0x1860 0x60>,
> + <&apps_smmu 0x18e0 0x00>,
> + <&apps_smmu 0x1900 0x00>,
> + <&apps_smmu 0x1980 0x20>,
> + <&apps_smmu 0x19a0 0x20>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "ife0",
> + "ife1",
> + "top";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> +
> camcc: clock-controller@ade0000 {
> compatible = "qcom,x1e80100-camcc";
> reg = <0 0x0ade0000 0 0x20000>;
>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: (subset) [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon
2025-01-02 16:32 [PATCH v3 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (5 preceding siblings ...)
2025-01-02 16:32 ` [PATCH v3 6/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
@ 2025-01-08 4:43 ` Bjorn Andersson
6 siblings, 0 replies; 13+ messages in thread
From: Bjorn Andersson @ 2025-01-08 4:43 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Michael Turquette, Stephen Boyd,
Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio,
Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Krzysztof Kozlowski, Konrad Dybcio
On Thu, 02 Jan 2025 16:32:05 +0000, Bryan O'Donoghue wrote:
> v3:
> - Fixes ordering of headers in dtsi - Vlad
> - Changes camcc to always on - Vlad
> - Applies RB as indicated - Krzysztof, Konrad
> - Link to v2: https://lore.kernel.org/r/20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-0-06fdd5a7d5bb@linaro.org
>
> v2:
>
> [...]
Applied, thanks!
[2/6] dt-bindings: clock: move qcom,x1e80100-camcc to its own file
commit: 7ec95ff9abf499b4775148db92528feb4e8ff1ee
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread