* [PATCH] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC
@ 2022-10-15 5:50 Matt Ranostay
2022-10-15 13:08 ` Krzysztof Kozlowski
0 siblings, 1 reply; 2+ messages in thread
From: Matt Ranostay @ 2022-10-15 5:50 UTC (permalink / raw)
To: peda, robh+dt, krzysztof.kozlowski+dt, vigneshr; +Cc: devicetree, Matt Ranostay
There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES
lane mux can select up to 4 different IPs. Define all the possible
functions.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
---
include/dt-bindings/mux/ti-serdes.h | 62 +++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
Related patchset series for j784s4 support:
Link: https://lore.kernel.org/linux-arm-kernel/20221014082314.118361-1-a-nandan@ti.com/
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index d3116c52ab72..669ca2d6abce 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -117,4 +117,66 @@
#define J721S2_SERDES0_LANE3_USB 0x2
#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
+/* J784S4 */
+
+#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
+#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
+#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J784S4_SERDES0_LANE3_USB 0x2
+#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
+#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
+#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
+#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
+#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
+#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
+#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
+#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
+#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
+#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
+#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
+#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
+#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
+#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
+#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
--
2.38.0.rc0.52.gdda7228a83
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC
2022-10-15 5:50 [PATCH] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC Matt Ranostay
@ 2022-10-15 13:08 ` Krzysztof Kozlowski
0 siblings, 0 replies; 2+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-15 13:08 UTC (permalink / raw)
To: Matt Ranostay, peda, robh+dt, krzysztof.kozlowski+dt, vigneshr; +Cc: devicetree
On 15/10/2022 01:50, Matt Ranostay wrote:
> There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES
> lane mux can select up to 4 different IPs. Define all the possible
> functions.
>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> ---
> include/dt-bindings/mux/ti-serdes.h | 62 +++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> Related patchset series for j784s4 support:
> Link: https://lore.kernel.org/linux-arm-kernel/20221014082314.118361-1-a-nandan@ti.com/
>
> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
> index d3116c52ab72..669ca2d6abce 100644
> --- a/include/dt-bindings/mux/ti-serdes.h
> +++ b/include/dt-bindings/mux/ti-serdes.h
> @@ -117,4 +117,66 @@
> #define J721S2_SERDES0_LANE3_USB 0x2
> #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
>
> +/* J784S4 */
> +
> +#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
You shouldn't store register values in the bindings. It's not their
purpose and there is no single need.
Although pattern already started here, so that's not a problem of this
patch:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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2022-10-15 5:50 [PATCH] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC Matt Ranostay
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