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Wed, 24 Sep 2025 11:43:09 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A0nVfrWCY5as Date: Wed, 24 Sep 2025 17:42:36 +0200 From: "Arnd Bergmann" To: "Manikanta Guntupalli" , "git (AMD-Xilinx)" , "Michal Simek" , "Alexandre Belloni" , "Frank Li" , "Rob Herring" , "krzk+dt@kernel.org" , "Conor Dooley" , =?UTF-8?Q?Przemys=C5=82aw_Gaj?= , "Wolfram Sang" , "tommaso.merciai.xr@bp.renesas.com" , "quic_msavaliy@quicinc.com" , "S-k, Shyam-sundar" , "Sakari Ailus" , "'billy_tsai@aspeedtech.com'" , "Kees Cook" , "Gustavo A. R. Silva" , "Jarkko Nikula" , "Jorge Marques" , "linux-i3c@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Linux-Arch , "linux-hardening@vger.kernel.org" Cc: "Pandey, Radhey Shyam" , "Goud, Srinivas" , "Datta, Shubhrajyoti" , "manion05gk@gmail.com" Message-Id: <295ee05e-3366-4846-9c8b-85ac09d79d48@app.fastmail.com> In-Reply-To: References: <20250923154551.2112388-1-manikanta.guntupalli@amd.com> <20250923154551.2112388-4-manikanta.guntupalli@amd.com> <13bbd85e-48d2-4163-b9f1-2a2a870d4322@app.fastmail.com> <4199b1ca-c1c7-41ef-b053-415f0cd80468@app.fastmail.com> <134c3a96-4023-47ab-8aa9-fd6ab75e5654@app.fastmail.com> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo() Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, Sep 24, 2025, at 17:23, Guntupalli, Manikanta wrote: >> Subject: Re: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo() >> > } >> > >> > With this approach, both little-endian and big-endian cases works as expected. >> >> This version should fix the cases where you have a big-endian kernel with either >> I3C_FIFO_BIG_ENDIAN or I3C_FIFO_LITTLE_ENDIAN, as neither combination >> does any byte swaps. >> >> However I'm fairly sure it's still broken for little-endian kernels when a driver asks for >> a I3C_FIFO_BIG_ENDIAN conversion, same as v7. > We tested using the I3C_FIFO_BIG_ENDIAN flag from the driver on > little-endian kernels, and it works as expected. Can you explain how that works? What I see is that your readsl_be()/writesl_be() functions do a byteswap on every four bytes, so the bytestream that gets copied to/from the FIFO gets garbled, in particular the final (unaligned) bytes of the kernel buffer end up in the higher bytes of the FIFO register rather than the first bytes as they do on a big-endian kernel. Are both the big-endian and little-endian kernels in your tests on microblaze, using the upstream version of asm/io.h? Is there a hardware byteswap between the CPU local bus and the i3c controller? If there is one, is it set the same way for both kernels? Arnd