[PATCH v3 0/2] Add NVIDIA VR144NVL board

[PATCH v3 0/2] Add NVIDIA VR144NVL board

[Donald Shannon]

Patch 1 adds the device tree binding for the NVIDIA VR144NVL board.
Patch 2 adds the device tree for the NVIDIA VR144NVL board.

This is an Aspeed AST2600 based BMC board for the NVIDIA VR144NVL
platform BMC.

Reference to Ast2600 SOC [1].
Reference to DC-SCM Spec [2].

Link: https://www.aspeedtech.com/server_ast2600/ [1]
Link: https://www.opencompute.org/w/index.php?title=Server/MHS/DC-SCM-Specs-and-Designs [2]

Signed-off-by: Donald Shannon <donalds@nvidia.com>

Donald Shannon (2):
  dt-bindings: arm: aspeed: Add NVIDIA VR144NVL board
  ARM: dts: aspeed: Add NVIDIA VR144NVL board

 .../bindings/arm/aspeed/aspeed.yaml           |   1 +
 arch/arm/boot/dts/aspeed/Makefile             |   1 +
 .../dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts | 778 ++++++++++++++++++
 3 files changed, 780 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts

-- 
2.43.0

[PATCH v3 1/2] dt-bindings: arm: aspeed: Add NVIDIA VR144NVL board

[Donald Shannon]

This is an Aspeed AST2600 based BMC board for the NVIDIA VR144NVL
platform.

Reference to Ast2600 SOC [1].
Reference to DC-SCM Spec [2].

Link: https://www.aspeedtech.com/server_ast2600/ [1]
Link: https://www.opencompute.org/w/index.php?title=Server/MHS/DC-SCM-Specs-and-Designs [2]

Signed-off-by: Donald Shannon <donalds@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v1 -> v2:
  - Received Acked-by from Conor Dooley
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index b3c9d3310d57..11e17e9ef15f 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -103,6 +103,7 @@ properties:
               - inventec,transformer-bmc
               - jabil,rbp-bmc
               - nvidia,gb200nvl-bmc
+              - nvidia,vr144nvl-bmc
               - qcom,dc-scm-v1-bmc
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc
-- 
2.43.0

[PATCH v3 2/2] ARM: dts: aspeed: Add NVIDIA VR144NVL board

[Donald Shannon]

This is an Aspeed AST2600 based BMC board for the NVIDIA VR144NVL
Platform.

Reference to Ast2600 SOC [1].
Reference to DC-SCM Spec [2].

Link: https://www.aspeedtech.com/server_ast2600/ [1]
Link: https://www.opencompute.org/w/index.php?title=Server/MHS/DC-SCM-Specs-and-Designs [2]

Signed-off-by: Donald Shannon <donalds@nvidia.com>
---
Changes v2 -> v3:
  - Changed to alphebetical order
  - Added comment that our flash layout is different because of our ROT
  - Removed unused phy-mode property from mac0
  - Renamed fault led gpio from input to output
---
 arch/arm/boot/dts/aspeed/Makefile             |   1 +
 .../dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts | 778 ++++++++++++++++++
 2 files changed, 779 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts

diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
index 8062c685f7e8..b479824c434b 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-lenovo-hr855xg2.dtb \
 	aspeed-bmc-microsoft-olympus.dtb \
 	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
+	aspeed-bmc-nvidia-vr144nvl.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
 	aspeed-bmc-opp-nicole.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts
new file mode 100644
index 000000000000..d7f11844246c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr144nvl.dts
@@ -0,0 +1,778 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "AST2600 VR144NVL BMC";
+	compatible = "nvidia,vr144nvl-bmc", "aspeed,ast2600";
+
+	aliases {
+		serial2 = &uart3;
+		serial4 = &uart5;
+		i2c16 = &c0uphy0;
+		i2c17 = &c0uphy2;
+		i2c24 = &c1uphy0;
+		i2c25 = &c1uphy2;
+		i2c32 = &i2c_usb_hub;
+		i2c33 = &i2c_tpm;
+		i2c34 = &i2c_dp;
+		i2c35 = &i2c_rtc;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button-power {
+			label = "power_btn";
+			linux,code = <KEY_POWER>;
+			gpios = <&exp7 9 GPIO_ACTIVE_LOW>;
+		};
+		button-uid {
+			label = "uid_btn";
+			linux,code = <KEY_FN_1>;
+			gpios = <&exp7 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		fault-led {
+			gpios = <&exp7 12 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_PANIC;
+			color = <LED_COLOR_ID_WHITE>;
+			label = "fault-led";
+			default-state = "off";
+			retain-state-suspended;
+			retain-state-shutdown;
+			panic-indicator;
+		};
+		hb-led {
+			gpios = <&gpio0 127 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_HEARTBEAT;
+			color = <LED_COLOR_ID_GREEN>;
+			label = "bmc-hbled";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+		pwr-led {
+			gpios = <&exp7 8 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
+			label = "pwr-led";
+			linux,default-trigger = "default-on";
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+		uid-led {
+			gpios = <&exp7 10 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_INDICATOR;
+			color = <LED_COLOR_ID_BLUE>;
+			label = "uid-led";
+			default-state = "off";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+		warn-led {
+			gpios = <&exp7 15 GPIO_ACTIVE_LOW>;
+			function = LED_FUNCTION_PANIC;
+			color = <LED_COLOR_ID_RED>;
+			label = "warn-led";
+			default-state = "off";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	reg_3v3_stby: regulator-3v3-standby {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3-standby";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vga_memory: framebuffer@9f000000 {
+			no-map;
+			reg = <0x9f000000 0x01000000>; /* 16M */
+		};
+
+		ramoops@a0000000 {
+			compatible = "ramoops";
+			reg = <0xa0000000 0x100000>; /* 1MB */
+			record-size = <0x10000>; /* 64KB */
+			max-reason = <2>; /* KMSG_DUMP_OOPS */
+		};
+
+		gfx_memory: framebuffer {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+		};
+
+		video_engine_memory: jpegbuffer {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x02000000>;	/* 32M */
+			alignment = <0x01000000>;
+		};
+	};
+};
+
+// USB Port B
+&ehci1 {
+	status = "okay";
+};
+
+// Need custom layout for Root of Trust
+&fmc {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		label = "bmc";
+		spi-max-frequency = <50000000>;
+		status = "okay";
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u-boot@0 {
+				// 896KB
+				reg = <0x0 0xe0000>;
+				label = "u-boot";
+			};
+
+			kernel@100000 {
+				// 9MB
+				reg = <0x100000 0x900000>;
+				label = "kernel";
+			};
+
+			rofs@a00000 {
+				// 55292KB (extends to end of 64MB SPI - 4KB)
+				reg = <0xa00000 0x35FF000>;
+				label = "rofs";
+			};
+		};
+	};
+};
+
+&gpio0 {
+	gpio-line-names =
+		/*A0-A7*/ "", "", "", "", "", "", "", "",
+		/*B0-B7*/ "", "", "", "", "", "", "", "",
+		/*C0-C7*/ "", "", "", "", "", "", "", "",
+		/*D0-D7*/ "", "", "", "", "", "", "", "",
+		/*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I",	"", "", "", "", "",
+					"MUX_SGPIO_SEL-O",
+		/*F0-F7*/ "", "", "", "", "", "", "", "",
+		/*G0-G7*/ "", "", "", "", "", "", "", "",
+		/*H0-H7*/ "", "", "", "", "", "", "", "",
+		/*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "", "BMC_DDR4_TEN-O",
+		/*J0-J7*/ "", "", "", "", "", "", "", "",
+		/*K0-K7*/ "", "", "", "", "", "", "", "",
+		/*L0-L7*/ "", "", "", "", "", "", "", "",
+		/*M0-M7*/ "HUB_RST_N-O", "BMC_FRU_WP-O", "SCM_PGOOD_C-O", "HPM_STBY_POWER_EN-O",
+					"STBY_POWER_PG_3V3-I", "PCIE_EP_RST_C_L-O", "", "",
+		/*N0-N7*/ "", "", "", "", "", "", "", "",
+		/*O0-O7*/ "", "", "", "", "", "", "", "",
+		/*P0-P7*/ "", "", "", "", "", "", "", "BMC_HBLED_L-O",
+		/*Q0-Q7*/ "", "", "", "", "", "", "", "",
+		/*R0-R7*/ "", "SP0_AP_INTR_N-I", "", "", "", "", "", "",
+		/*S0-S7*/ "", "", "", "", "", "", "", "",
+		/*T0-T7*/ "", "", "", "", "", "", "", "",
+		/*U0-U7*/ "", "", "", "", "", "", "", "",
+		/*V0-V7*/ "", "", "", "","PCB_TEMP_ALERT_L-I", "","", "",
+		/*W0-W7*/ "", "", "", "", "", "", "", "",
+		/*X0-X7*/ "", "", "", "", "", "", "", "",
+		/*Y0-Y7*/ "", "", "", "EMMC_RST_L-O", "","", "", "",
+		/*Z0-Z7*/ "GPIOZ0_EROT_OOB_INTR_N_C-I","", "", "", "", "", "", "";
+};
+
+&gpio1 {
+	/* 36 1.8V GPIOs */
+	gpio-line-names =
+		/*A0-A7*/ "", "", "", "", "", "", "", "",
+		/*B0-B7*/ "", "", "", "", "AP_EROT_REQ-O", "EROT_AP_GNT-I", "I2C_MGMT0_ALERT_N-I",
+					"",
+		/*C0-C7*/ "", "", "", "", "", "", "", "",
+		/*D0-D7*/ "", "", "", "", "", "", "", "I2C_SSIF_ALERT_N-I",
+		/*E0-E7*/ "", "", "", "", "", "", "", "";
+};
+
+// I2C1
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C2
+// Baseboard 0 Management 1
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+		vdd-supply = <&reg_3v3_stby>;
+
+		c0uphy0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		c0uphy2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+	};
+
+	exp0: gpio@20 {
+		compatible = "nxp,pca9535";
+		reg = <0x20>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"MCU_RESET_L-O",
+			"MCU_RECOVERY_L-O",
+			"GPU_MCU_RESET_L_3V3-O",
+			"GPU_MCU_RECOVERY_L_3V3-O",
+			"THERM_OVERT_L-I",
+			"THERM_WARN_L-I",
+			"HMC_IST_PRE_RST_L-O",
+			"CPLD_READY-I",
+			"MODULE_PWR_GOOD-I",
+			"MCU_HMC_ALERT_L-I",
+			"USB_HMC_HUB_RST_L-O",
+			"HPM_MCU_OK-I",
+			"CPU0_SHDN_OK_L_3V3-I",
+			"PRIMARY_NODE_L-O",
+			"IST_SYS_RST_L-O",
+			"PWR_BRAKE_STATUS_L-I";
+	};
+
+	exp1: gpio@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"CPU_FORCED_RECOVERY_L-O",
+			"CPU_BOOT_DEV_SEL0-O",
+			"CPU_BOOT_DEV_SEL1-O",
+			"CPU_BOOT_DEV_SEL2-O",
+			"BOARD_ID_0-I",
+			"CPU_RECOVERY_TYPE0-O",
+			"CPU_RECOVERY_TYPE1-O",
+			"CPU_IST_BOOT_HMC-O",
+			"CPU_BOOT_CHAIN0-O",
+			"BOARD_ID_1-I",
+			"BOARD_ID_2-I",
+			"CPU_DIE_SEL0-O",
+			"CPU_DIE_SEL1-O",
+			"CPU_DIE_SEL2-O",
+			"CPU_BOOT_COMPLETE-I",
+			"IOX_JTAG_NVSEL-O";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+// I2C3
+// Baseboard 0 Management 0
+&i2c2 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	exp3: gpio@20 {
+		compatible = "nxp,pca9535";
+		reg = <0x20>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"BMC_SHDN_FORCE_L-O",
+			"IOX_STBY_PWR_PGOOD-I",
+			"THERM_OVERT_L-I",
+			"THERM_WARN_L-I",
+			"GLOBAL_WP_BMC-O",
+			"USB_HUB0_RST_L-O",
+			"IOX_PRE_RST_N-O",
+			"LEAK_DETECT_L-I",
+			"RUN_PWR_EN-O",
+			"MODULE_PWR_GOOD-I",
+			"CPU_CHIPTHROT_L_3V3-I",
+			"SHDN_REQ_L_3V3-O",
+			"CPU0_SHDN_OK_L_3V3-I",
+			"CPU1_SHDN_OK_L_3V3-I",
+			"PWR_BRAKE_L_3V3-O",
+			"PWR_BRAKE_STATUS_L-I";
+	};
+
+	exp4: gpio@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"I2C_BUS_MUX_RST_L-O",
+			"HPM_MCU_OK-I",
+			"AIC_USB_EN-O",
+			"SOCAMM_DAC_SEL0-O",
+			"SNN_SOCAMM_DAC_SEL1-O",
+			"C0_SOCAMM_I2C_SEL_R-O",
+			"SNN_C1_SOCAMM_I2C_SEL_R-O",
+			"EEPROM_POWER_DISABLE-O",
+			"CPU_L0L1_RST_L_3V3-I",
+			"CPU_L2_RST_L_3V3-I",
+			"BOARD_ID_0-I",
+			"BOARD_ID_1-I",
+			"BMC_LEAK_TEST_L-O",
+			"MCU_BMC_ALERT_L-I",
+			"CPU_BOOT_COMPLETE_3V3-I",
+			"BOARD_ID_2-I";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+// I2C4
+// Baseboard 1 Management 1
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+		vdd-supply = <&reg_3v3_stby>;
+
+		c1uphy0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		c1uphy2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+	};
+
+	exp5: gpio@20 {
+		compatible = "nxp,pca9535";
+		reg = <0x20>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"MCU_RESET_L_C1-O",
+			"MCU_RECOVERY_L_C1-O",
+			"GPU_MCU_RESET_L_3V3_C1-O",
+			"GPU_MCU_RECOVERY_L_3V3_C1-O",
+			"THERM_OVERT_L_C1-I",
+			"THERM_WARN_L_C1-I",
+			"HMC_IST_PRE_RST_L_C1-O",
+			"CPLD_READY_C1-I",
+			"MODULE_PWR_GOOD_C1-I",
+			"MCU_HMC_ALERT_L_C1-I",
+			"USB_HMC_HUB_RST_L_C1-O",
+			"HPM_MCU_OK_C1-I",
+			"CPU0_SHDN_OK_L_3V3_C1-I",
+			"PRIMARY_NODE_L_C1-O",
+			"IST_SYS_RST_L_C1-O",
+			"PWR_BRAKE_STATUS_L_C1-I";
+	};
+
+	exp6: gpio@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"CPU_FORCED_RECOVERY_L_C1-O",
+			"CPU_BOOT_DEV_SEL0_C1-O",
+			"CPU_BOOT_DEV_SEL1_C1-O",
+			"CPU_BOOT_DEV_SEL2_C1-O",
+			"BOARD_ID_0_C1-I",
+			"CPU_RECOVERY_TYPE0_C1-O",
+			"CPU_RECOVERY_TYPE1_C1-O",
+			"CPU_IST_BOOT_HMC_C1-O",
+			"CPU_BOOT_CHAIN0_C1-O",
+			"BOARD_ID_1_C1-I",
+			"BOARD_ID_2_C1-I",
+			"CPU_DIE_SEL0_C1-O",
+			"CPU_DIE_SEL1_C1-O",
+			"CPU_DIE_SEL2_C1-O",
+			"CPU_BOOT_COMPLETE_C1-I",
+			"IOX_JTAG_NVSEL_C1-O";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+// I2C5
+&i2c4 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C6
+// Management Board
+&i2c5 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	exp7: gpio@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"HMC_RST_R_L-O",
+			"HMC_RECOVERY_R-O",
+			"HMC_SPI_MUX_R_SEL-O",
+			"GLOBAL_WP-O",
+			"HMC_READY-I",
+			"HMC_PRSNT_R-I",
+			"BMC_SELF_PWR_CYCLE-O",
+			"EEDO_LED2-O",
+			"PWR_LED_L-O",
+			"PWR_BTN_L-I",
+			"UID_LED_L-O",
+			"UID_BTN_L-I",
+			"FAULT_LED_L-0",
+			"USB2_HUB_RST_L-O",
+			"BMC_M2_RST_L-O",
+			"WARN_LED_L-O";
+	};
+
+	temp-sensor@48 {
+		compatible = "ti,tmp1075";
+		reg = <0x48>;
+	};
+};
+
+// I2C7
+// BMC Expander + Management Board
+&i2c6 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	exp8: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-line-names =
+			"",
+			"",
+			"EROT_FATAL_ERROR_N-I",
+			"",
+			"",
+			"EROT_RECOV_N-O",
+			"NRESET_IN_IOX_N-O",
+			"";
+	};
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9546";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+		vdd-supply = <&reg_3v3_stby>;
+
+		i2c_usb_hub:i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+
+		i2c_tpm:i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+		};
+
+		i2c_dp:i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+
+		i2c_rtc:i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
+};
+
+// I2C8
+// Baseboard 1 Management 0
+&i2c7 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	exp9: gpio@20 {
+		compatible = "nxp,pca9535";
+		reg = <0x20>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"BMC_SHDN_FORCE_L_C1-O",
+			"IOX_STBY_PWR_PGOOD_C1-I",
+			"THERM_OVERT_L_C1-I",
+			"THERM_WARN_L_C1-I",
+			"GLOBAL_WP_BMC_C1-O",
+			"USB_HUB0_RST_L_C1-O",
+			"IOX_PRE_RST_N_C1-O",
+			"LEAK_DETECT_L_C1-I",
+			"RUN_PWR_EN_C1-O",
+			"MODULE_PWR_GOOD_C1-I",
+			"CPU_CHIPTHROT_L_3V3_C1-I",
+			"SHDN_REQ_L_3V3_C1-O",
+			"CPU0_SHDN_OK_L_3V3_C1-I",
+			"CPU1_SHDN_OK_L_3V3_C1-I",
+			"PWR_BRAKE_L_3V3_C1-O",
+			"PWR_BRAKE_STATUS_L_C1-I";
+	};
+
+	exp10: gpio@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vcc-supply = <&reg_3v3_stby>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"I2C_BUS_MUX_RST_L_C1-O",
+			"HPM_MCU_OK_C1-I",
+			"AIC_USB_EN_C1-O",
+			"SOCAMM_DAC_SEL0_C1-O",
+			"SNN_SOCAMM_DAC_SEL1_C1-O",
+			"C0_SOCAMM_I2C_SEL_R_C1-O",
+			"SNN_C1_SOCAMM_I2C_SEL_R_C1-O",
+			"EEPROM_POWER_DISABLE_C1-O",
+			"CPU_L0L1_RST_L_3V3_C1-I",
+			"CPU_L2_RST_L_3V3_C1-I",
+			"BOARD_ID_0_C1-I",
+			"BOARD_ID_1_C1-I",
+			"BMC_LEAK_TEST_L_C1-O",
+			"MCU_BMC_ALERT_L_C1-I",
+			"CPU_BOOT_COMPLETE_3V3_C1-I",
+			"BOARD_ID_2_C1-I";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+// I2C9
+&i2c8 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C10
+&i2c9 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C11
+// BMC FRU + TEMP
+&i2c10 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	temp-sensor@48 {
+		compatible = "ti,tmp1075";
+		reg = <0x48>;
+	};
+
+};
+
+// I2C13
+&i2c12 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C14
+&i2c13 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C15
+&i2c14 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+// I2C16
+&i2c15 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&mac0 {
+	pinctrl-names = "default";
+	phy-handle = <&ethphy0>;
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi2_default>;
+	status = "okay";
+	// Data SPI is 64MB in size
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		label = "config";
+		spi-max-frequency = <50000000>;
+		status = "okay";
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u-boot-env@0 {
+				// 256KB
+				reg = <0x0 0x40000>;
+				label = "u-boot-env";
+			};
+
+			rwfs@40000 {
+				// 16MB
+				reg = <0x40000 0x1000000>;
+				label = "rwfs";
+			};
+
+			log@1040000 {
+				// 40MB
+				reg = <0x1040000 0x2800000>;
+				label = "log";
+			};
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+// USB Port B
+&uhci {
+	status = "okay";
+};
+
+// USB port A
+&vhub {
+	status = "okay";
+};
+
+&video {
+	memory-region = <&video_engine_memory>;
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v3 2/2] ARM: dts: aspeed: Add NVIDIA VR144NVL board

[Andrew Lunn]

> Changes v2 -> v3:
>   - Removed unused phy-mode property from mac0

> +&mac0 {
> +	pinctrl-names = "default";
> +	phy-handle = <&ethphy0>;
> +	pinctrl-0 = <&pinctrl_rgmii1_default>;
> +	status = "okay";
> +};

Oh, fun.

Please don't do that. At some point Aspeed it going to clean up the
mess they made with RGMII delays. And at that point, it is very likely
your board will mysteriously break, if nobody remembers it is doing
something probably no other board does.

	Andrew

Re: [PATCH v3 2/2] ARM: dts: aspeed: Add NVIDIA VR144NVL board

[Donald Shannon]

On 9/10/25 05:56, Andrew Lunn wrote:

>> Changes v2 -> v3:
>>    - Removed unused phy-mode property from mac0
>> +&mac0 {
>> +     pinctrl-names = "default";
>> +     phy-handle = <&ethphy0>;
>> +     pinctrl-0 = <&pinctrl_rgmii1_default>;
>> +     status = "okay";
>> +};
> Oh, fun.
>
> Please don't do that. At some point Aspeed it going to clean up the
> mess they made with RGMII delays. And at that point, it is very likely
> your board will mysteriously break, if nobody remembers it is doing
> something probably no other board does.
>
>          Andrew

Hi Andrew,

I will add it back in. Our board phy has tx and rx delays.

Don