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From: Devarsh Thakkar <devarsht@ti.com>
To: Harikrishna Shenoy <h-shenoy@ti.com>, <robh@kernel.org>,
	<Laurent.pinchart@ideasonboard.com>, <airlied@gmail.com>,
	<andrzej.hajda@intel.com>, <conor+dt@kernel.org>,
	<devicetree@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
	<jernej.skrabec@gmail.com>, <jonas@kwiboo.se>,
	<krzk+dt@kernel.org>, <linux-kernel@vger.kernel.org>,
	<maarten.lankhorst@linux.intel.com>, <mripard@kernel.org>,
	<neil.armstrong@linaro.org>, <rfoss@kernel.org>, <s-jain1@ti.com>,
	<simona@ffwll.ch>, <sjakhade@cadence.com>, <tzimmermann@suse.de>,
	<u-kumar1@ti.com>, <yamonkar@cadence.com>, <pthombar@cadence.com>,
	<nm@ti.com>
Subject: Re: [PATCH v4] dt-bindings: drm/bridge: Update reg-name and reg
Date: Mon, 21 Sep 2026 21:08:35 +0530	[thread overview]
Message-ID: <29e041a2-7c60-44c3-8735-de110dbc2e62@ti.com> (raw)
In-Reply-To: <20251126092949.298530-1-h-shenoy@ti.com>

On 26/11/25 14:59, Harikrishna Shenoy wrote:
> Move register name constraints and reg description lists to appropriate
> compatibility sections to ensure correct register names are used with each
> compatible value. The j721e-integ registers are specific to TI SoCs and not
> required for other compatibles.
> 
> Add DSC register descriptions to align bindings with hardware capabilities.
> Structure the reg and reg-names constraints as lists according to
> compatibles using oneOf schema construct.
> 
> Fixes: 7169d082e7e6 ("dt-bindings: drm/bridge: MHDP8546 bridge binding changes for HDCP")
> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>

Reviewed-by: Devarsh Thakkar <devarsht@ti.com>

Regards
Devarsh

> ---
> 
> Links to some discussions pointing to need for a fixes patch:
> https://lore.kernel.org/all/20250903220312.GA2903503-robh@kernel.org/
> https://lore.kernel.org/all/d2367789-6b54-4fc2-bb7c-609c0fe084d3@ti.com/
> 
> Link to v3:
> <https://lore.kernel.org/all/20251121123437.860390-1-h-shenoy@ti.com/>
> 
> Changelog v3 --> v4:
> - Update top level constraints and commit message.
> - Update logs with processed schema- https://gist.github.com/h-shenoy/a422f7278859cd95447e674963caabd9
> 
> Link to v2:
> <https://lore.kernel.org/all/20251119122447.514729-1-h-shenoy@ti.com/>
> 
> Changelog v2 --> v3:
> -Add the reg description list and reg-name list in top level constraints
> using oneOf for either of compatible.
> Logs after testing some cases: https://gist.github.com/h-shenoy/a422f7278859cd95447e674963caabd9
> 
> Link to v1:
> <https://lore.kernel.org/all/20251107131535.1841393-1-h-shenoy@ti.com/>
> 
> Changelog v1 --> v2:
> -Update the reg description list for each compatible and add register space
> for dsc to make the bindings reflect what hardware supports although
> the driver doesn't support dsc yet.
> 
> Note: j721e-integ are not optional registers for ti-compatible.
> 
>   .../display/bridge/cdns,mhdp8546.yaml         | 85 ++++++++++++++-----
>   1 file changed, 66 insertions(+), 19 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
> index c2b369456e4e2..4cec0f4c22a2b 100644
> --- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
> @@ -17,23 +17,45 @@ properties:
>         - ti,j721e-mhdp8546
>   
>     reg:
> -    minItems: 1
> -    items:
> -      - description:
> -          Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
> -          The AUX and PMA registers are not part of this range, they are instead
> -          included in the associated PHY.
> -      - description:
> -          Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
> -      - description:
> -          Register block of mhdptx sapb registers.
> +    oneOf:
> +      - items:
> +          - description:
> +              Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
> +              The AUX and PMA registers are not part of this range, they are instead
> +              included in the associated PHY.
> +          - description:
> +              Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
> +          - description:
> +              Register block of mhdptx sapb registers.
> +          - description:
> +              Register block for mhdptx DSC encoder registers.
> +        minItems: 2
> +
> +      - items:
> +          - description:
> +              Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
> +              The AUX and PMA registers are not part of this range, they are instead
> +              included in the associated PHY.
> +          - description:
> +              Register block of mhdptx sapb registers.
> +          - description:
> +              Register block for mhdptx DSC encoder registers.
> +        minItems: 1
>   
>     reg-names:
> -    minItems: 1
> -    items:
> -      - const: mhdptx
> -      - const: j721e-intg
> -      - const: mhdptx-sapb
> +    oneOf:
> +      - items:
> +          - const: mhdptx
> +          - const: j721e-intg
> +          - const: mhdptx-sapb
> +          - const: dsc
> +        minItems: 2
> +
> +      - items:
> +          - const: mhdptx
> +          - const: mhdptx-sapb
> +          - const: dsc
> +        minItems: 1
>   
>     clocks:
>       maxItems: 1
> @@ -100,18 +122,43 @@ allOf:
>         properties:
>           reg:
>             minItems: 2
> -          maxItems: 3
> +          items:
> +            - description:
> +                Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
> +                The AUX and PMA registers are not part of this range, they are instead
> +                included in the associated PHY.
> +            - description:
> +                Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
> +            - description:
> +                Register block of mhdptx sapb registers.
> +            - description:
> +                Register block for mhdptx DSC encoder registers.
>           reg-names:
>             minItems: 2
> -          maxItems: 3
> +          items:
> +            - const: mhdptx
> +            - const: j721e-intg
> +            - const: mhdptx-sapb
> +            - const: dsc
>       else:
>         properties:
>           reg:
>             minItems: 1
> -          maxItems: 2
> +          items:
> +            - description:
> +                Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
> +                The AUX and PMA registers are not part of this range, they are instead
> +                included in the associated PHY.
> +            - description:
> +                Register block of mhdptx sapb registers.
> +            - description:
> +                Register block for mhdptx DSC encoder registers.
>           reg-names:
>             minItems: 1
> -          maxItems: 2
> +          items:
> +            - const: mhdptx
> +            - const: mhdptx-sapb
> +            - const: dsc
>   
>   required:
>     - compatible


      parent reply	other threads:[~2026-09-21 15:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-26  9:29 [PATCH v4] dt-bindings: drm/bridge: Update reg-name and reg Harikrishna Shenoy
2025-12-03  7:57 ` Krzysztof Kozlowski
2026-09-21 15:38 ` Devarsh Thakkar [this message]

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