* [PATCH RFC 01/11] arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 02/11] arm64: dts: qcom: sc7180: " Konrad Dybcio
` (12 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 642ca8f0236b3944c5962e5b12b5959cd349812f..1dd760e97794877bae35d19ca264f8fc70f96c8b 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1412,6 +1412,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
intc: interrupt-controller@17200000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 01/11] arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-20 13:44 ` Doug Anderson
2024-09-18 22:57 ` [PATCH RFC 03/11] arm64: dts: qcom: sc8180x: " Konrad Dybcio
` (11 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index b5ebf89803251203a8d38f6a4690aa052a9e8e61..ed258b4ab486af1765b882164962c56935210898 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3625,6 +3625,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
intc: interrupt-controller@17a00000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH RFC 02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 ` [PATCH RFC 02/11] arm64: dts: qcom: sc7180: " Konrad Dybcio
@ 2024-09-20 13:44 ` Doug Anderson
0 siblings, 0 replies; 21+ messages in thread
From: Doug Anderson @ 2024-09-20 13:44 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, Marijn Suijten, linux-arm-msm, devicetree,
linux-kernel, Konrad Dybcio, Rob Clark
Hi,
On Wed, Sep 18, 2024 at 3:58 PM 'Konrad Dybcio' via
cros-qcom-dts-watchers <cros-qcom-dts-watchers@chromium.org> wrote:
>
> From: Konrad Dybcio <quic_kdybcio@quicinc.com>
>
> On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
FWIW, the "RPMh-based" confused me a bit. This isn't really related to
RPMh, right? I think you're just using "RPMh-based" to establish a
point in time and that Qualcomm added RPMh in the same generation of
SoCs that they added cache-coherent pagetable walk?
> pagetable walk via the IDR0 register. This however is not respected by
> the arm-smmu driver unless dma-coherent is set.
>
> Mark the node as dma-coherent to ensure this (and other) implementations
> take this coherency into account.
>
> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
> 1 file changed, 1 insertion(+)
I remotely booted this on sc7180-trogdor-lazor. Since I'm working
remotely at the moment I can't check the screen, but I can at least
confirm that nothing seemed to go boom. I can also confirm that
without your patch I see:
[ 1.580607] arm-smmu 15000000.iommu: non-coherent table walk
[ 1.580612] arm-smmu 15000000.iommu: (IDR0.CTTW overridden
by FW configuration)
...and after your patch I see:
[ 1.569350] arm-smmu 15000000.iommu: coherent table walk
Thus:
Tested-by: Douglas Anderson <dianders@chromium.org>
I'm curious: can this also be turned on for the Adreno SMMU also?
dmesg still has this after your patch (which makes sense since your
patch didn't touch the Adreno SMMU):
[ 2.423521] arm-smmu 5040000.iommu: non-coherent table walk
[ 2.423526] arm-smmu 5040000.iommu: (IDR0.CTTW overridden by FW
configuration)
-Doug
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC 03/11] arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 01/11] arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 02/11] arm64: dts: qcom: sc7180: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 04/11] arm64: dts: qcom: sc8280xp: " Konrad Dybcio
` (10 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 0e9429684dd97bc2d93185815b29e9db0fad892b..e80e0d3b77329836ec3c97e707c5659b9ad83325 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3662,7 +3662,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
-
+ dma-coherent;
};
remoteproc_adsp: remoteproc@17300000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 04/11] arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (2 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 03/11] arm64: dts: qcom: sc8180x: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 05/11] arm64: dts: qcom: sdm670: " Konrad Dybcio
` (9 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 80a57aa228397e23e3e2d5643c0b563a60d71170..d36f677ae4cd857388dcd5821160a6472a0904b4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -5008,6 +5008,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
intc: interrupt-controller@17a00000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 05/11] arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (3 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 04/11] arm64: dts: qcom: sc8280xp: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 06/11] arm64: dts: qcom: sdm845: " Konrad Dybcio
` (8 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 187c6698835d34e617aeb83309b6d5926eb57198..a08a64bc033ffdea283645c6bf4ed835a59c3366 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1737,6 +1737,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
gladiator_noc: interconnect@17900000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 06/11] arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (4 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 05/11] arm64: dts: qcom: sdm670: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 07/11] arm64: dts: qcom: sm6350: " Konrad Dybcio
` (7 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 54077549b9da7f0ece69a01d370692d9d716bbb5..49440d1b2cf6caf6da9d97c635cbd751f0700326 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5159,6 +5159,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
anoc_1_tbu: tbu@150c5000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (5 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 06/11] arm64: dts: qcom: sdm845: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-24 7:15 ` Luca Weiss
2024-09-18 22:57 ` [PATCH RFC 08/11] arm64: dts: qcom: sm8150: " Konrad Dybcio
` (6 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 7986ddb30f6e8ce6ceeb0f90772b0243aed6bffe..54cfe99006613f8ccc5bf6d83bcb4bf8e72f3cfe 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2685,6 +2685,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
intc: interrupt-controller@17a00000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH RFC 07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 ` [PATCH RFC 07/11] arm64: dts: qcom: sm6350: " Konrad Dybcio
@ 2024-09-24 7:15 ` Luca Weiss
2024-09-24 7:37 ` Luca Weiss
0 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2024-09-24 7:15 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
> From: Konrad Dybcio <quic_kdybcio@quicinc.com>
>
> On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
> pagetable walk via the IDR0 register. This however is not respected by
> the arm-smmu driver unless dma-coherent is set.
>
> Mark the node as dma-coherent to ensure this (and other) implementations
> take this coherency into account.
Hi Konrad!
Similar to [0] everything seems to look fine on SM7225 Fairphone 4.
[ 0.190433] arm-smmu 15000000.iommu: probing hardware configuration...
[ 0.190459] arm-smmu 15000000.iommu: SMMUv2 with:
[ 0.190499] arm-smmu 15000000.iommu: stage 1 translation
[ 0.190515] arm-smmu 15000000.iommu: coherent table walk
[ 0.190531] arm-smmu 15000000.iommu: stream matching with 71 register groups
[ 0.190560] arm-smmu 15000000.iommu: 63 context banks (0 stage-2 only)
[ 0.191097] arm-smmu 15000000.iommu: Supported page sizes: 0x61311000
[ 0.191114] arm-smmu 15000000.iommu: Stage-1: 36-bit VA -> 36-bit IPA
[ 0.191299] arm-smmu 15000000.iommu: preserved 0 boot mappings
The Adreno SMMU still has non-coherent table walk.
[ 1.141215] arm-smmu 3d40000.iommu: probing hardware configuration...
[ 1.141243] arm-smmu 3d40000.iommu: SMMUv2 with:
[ 1.141270] arm-smmu 3d40000.iommu: stage 1 translation
[ 1.141279] arm-smmu 3d40000.iommu: address translation ops
[ 1.141288] arm-smmu 3d40000.iommu: non-coherent table walk
[ 1.141296] arm-smmu 3d40000.iommu: (IDR0.CTTW overridden by FW configuration)
[ 1.141307] arm-smmu 3d40000.iommu: stream matching with 5 register groups
[ 1.141326] arm-smmu 3d40000.iommu: 5 context banks (0 stage-2 only)
[ 1.141347] arm-smmu 3d40000.iommu: Supported page sizes: 0x63315000
[ 1.141356] arm-smmu 3d40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
[ 1.141568] arm-smmu 3d40000.iommu: preserved 0 boot mappings
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
[0] https://lore.kernel.org/linux-arm-msm/CAD=FV=Xrbe1NO+trk1SJ30gHm5jLFjd0bAeG3H46gD+vNFZa1w@mail.gmail.com/
Regards
Luca
>
> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 7986ddb30f6e8ce6ceeb0f90772b0243aed6bffe..54cfe99006613f8ccc5bf6d83bcb4bf8e72f3cfe 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -2685,6 +2685,7 @@ apps_smmu: iommu@15000000 {
> <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> };
>
> intc: interrupt-controller@17a00000 {
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH RFC 07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
2024-09-24 7:15 ` Luca Weiss
@ 2024-09-24 7:37 ` Luca Weiss
2024-09-24 10:04 ` Konrad Dybcio
0 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2024-09-24 7:37 UTC (permalink / raw)
To: Luca Weiss, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On Tue Sep 24, 2024 at 9:15 AM CEST, Luca Weiss wrote:
> On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
> > From: Konrad Dybcio <quic_kdybcio@quicinc.com>
> >
> > On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
> > pagetable walk via the IDR0 register. This however is not respected by
> > the arm-smmu driver unless dma-coherent is set.
> >
> > Mark the node as dma-coherent to ensure this (and other) implementations
> > take this coherency into account.
>
> Hi Konrad!
>
> Similar to [0] everything seems to look fine on SM7225 Fairphone 4.
>
> [ 0.190433] arm-smmu 15000000.iommu: probing hardware configuration...
> [ 0.190459] arm-smmu 15000000.iommu: SMMUv2 with:
> [ 0.190499] arm-smmu 15000000.iommu: stage 1 translation
> [ 0.190515] arm-smmu 15000000.iommu: coherent table walk
> [ 0.190531] arm-smmu 15000000.iommu: stream matching with 71 register groups
> [ 0.190560] arm-smmu 15000000.iommu: 63 context banks (0 stage-2 only)
> [ 0.191097] arm-smmu 15000000.iommu: Supported page sizes: 0x61311000
> [ 0.191114] arm-smmu 15000000.iommu: Stage-1: 36-bit VA -> 36-bit IPA
> [ 0.191299] arm-smmu 15000000.iommu: preserved 0 boot mappings
>
> The Adreno SMMU still has non-coherent table walk.
>
> [ 1.141215] arm-smmu 3d40000.iommu: probing hardware configuration...
> [ 1.141243] arm-smmu 3d40000.iommu: SMMUv2 with:
> [ 1.141270] arm-smmu 3d40000.iommu: stage 1 translation
> [ 1.141279] arm-smmu 3d40000.iommu: address translation ops
> [ 1.141288] arm-smmu 3d40000.iommu: non-coherent table walk
> [ 1.141296] arm-smmu 3d40000.iommu: (IDR0.CTTW overridden by FW configuration)
> [ 1.141307] arm-smmu 3d40000.iommu: stream matching with 5 register groups
> [ 1.141326] arm-smmu 3d40000.iommu: 5 context banks (0 stage-2 only)
> [ 1.141347] arm-smmu 3d40000.iommu: Supported page sizes: 0x63315000
> [ 1.141356] arm-smmu 3d40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
> [ 1.141568] arm-smmu 3d40000.iommu: preserved 0 boot mappings
>
>
> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
>
> [0] https://lore.kernel.org/linux-arm-msm/CAD=FV=Xrbe1NO+trk1SJ30gHm5jLFjd0bAeG3H46gD+vNFZa1w@mail.gmail.com/
FWIW adding 'dma-coherent;' to &adreno_smmu also doesn't seem to
explode:
[ 1.451965] arm-smmu 3d40000.iommu: probing hardware configuration...
[ 1.455547] arm-smmu 3d40000.iommu: SMMUv2 with:
[ 1.459041] arm-smmu 3d40000.iommu: stage 1 translation
[ 1.462446] arm-smmu 3d40000.iommu: address translation ops
[ 1.465843] arm-smmu 3d40000.iommu: coherent table walk
[ 1.469216] arm-smmu 3d40000.iommu: stream matching with 5 register groups
[ 1.472645] arm-smmu 3d40000.iommu: 5 context banks (0 stage-2 only)
[ 1.476067] arm-smmu 3d40000.iommu: Supported page sizes: 0x63315000
[ 1.479458] arm-smmu 3d40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
[ 1.483152] arm-smmu 3d40000.iommu: preserved 0 boot mappings
And kmscube still runs as expected.
Regards
Luca
>
> Regards
> Luca
>
> >
> > Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > index 7986ddb30f6e8ce6ceeb0f90772b0243aed6bffe..54cfe99006613f8ccc5bf6d83bcb4bf8e72f3cfe 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> > @@ -2685,6 +2685,7 @@ apps_smmu: iommu@15000000 {
> > <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > };
> >
> > intc: interrupt-controller@17a00000 {
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH RFC 07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
2024-09-24 7:37 ` Luca Weiss
@ 2024-09-24 10:04 ` Konrad Dybcio
0 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-24 10:04 UTC (permalink / raw)
To: Luca Weiss, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 24.09.2024 9:37 AM, Luca Weiss wrote:
> On Tue Sep 24, 2024 at 9:15 AM CEST, Luca Weiss wrote:
>> On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <quic_kdybcio@quicinc.com>
>>>
>>> On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
>>> pagetable walk via the IDR0 register. This however is not respected by
>>> the arm-smmu driver unless dma-coherent is set.
>>>
>>> Mark the node as dma-coherent to ensure this (and other) implementations
>>> take this coherency into account.
>>
>> Hi Konrad!
>>
>> Similar to [0] everything seems to look fine on SM7225 Fairphone 4.
>>
>> [ 0.190433] arm-smmu 15000000.iommu: probing hardware configuration...
>> [ 0.190459] arm-smmu 15000000.iommu: SMMUv2 with:
>> [ 0.190499] arm-smmu 15000000.iommu: stage 1 translation
>> [ 0.190515] arm-smmu 15000000.iommu: coherent table walk
>> [ 0.190531] arm-smmu 15000000.iommu: stream matching with 71 register groups
>> [ 0.190560] arm-smmu 15000000.iommu: 63 context banks (0 stage-2 only)
>> [ 0.191097] arm-smmu 15000000.iommu: Supported page sizes: 0x61311000
>> [ 0.191114] arm-smmu 15000000.iommu: Stage-1: 36-bit VA -> 36-bit IPA
>> [ 0.191299] arm-smmu 15000000.iommu: preserved 0 boot mappings
>>
>> The Adreno SMMU still has non-coherent table walk.
>>
>> [ 1.141215] arm-smmu 3d40000.iommu: probing hardware configuration...
>> [ 1.141243] arm-smmu 3d40000.iommu: SMMUv2 with:
>> [ 1.141270] arm-smmu 3d40000.iommu: stage 1 translation
>> [ 1.141279] arm-smmu 3d40000.iommu: address translation ops
>> [ 1.141288] arm-smmu 3d40000.iommu: non-coherent table walk
>> [ 1.141296] arm-smmu 3d40000.iommu: (IDR0.CTTW overridden by FW configuration)
>> [ 1.141307] arm-smmu 3d40000.iommu: stream matching with 5 register groups
>> [ 1.141326] arm-smmu 3d40000.iommu: 5 context banks (0 stage-2 only)
>> [ 1.141347] arm-smmu 3d40000.iommu: Supported page sizes: 0x63315000
>> [ 1.141356] arm-smmu 3d40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
>> [ 1.141568] arm-smmu 3d40000.iommu: preserved 0 boot mappings
>>
>>
>> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
>>
>> [0] https://lore.kernel.org/linux-arm-msm/CAD=FV=Xrbe1NO+trk1SJ30gHm5jLFjd0bAeG3H46gD+vNFZa1w@mail.gmail.com/
>
> FWIW adding 'dma-coherent;' to &adreno_smmu also doesn't seem to
> explode:
>
> [ 1.451965] arm-smmu 3d40000.iommu: probing hardware configuration...
> [ 1.455547] arm-smmu 3d40000.iommu: SMMUv2 with:
> [ 1.459041] arm-smmu 3d40000.iommu: stage 1 translation
> [ 1.462446] arm-smmu 3d40000.iommu: address translation ops
> [ 1.465843] arm-smmu 3d40000.iommu: coherent table walk
> [ 1.469216] arm-smmu 3d40000.iommu: stream matching with 5 register groups
> [ 1.472645] arm-smmu 3d40000.iommu: 5 context banks (0 stage-2 only)
> [ 1.476067] arm-smmu 3d40000.iommu: Supported page sizes: 0x63315000
> [ 1.479458] arm-smmu 3d40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
> [ 1.483152] arm-smmu 3d40000.iommu: preserved 0 boot mappings
>
> And kmscube still runs as expected.
Thanks, I'll look into adreno separately
Konrad
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH RFC 08/11] arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (6 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 07/11] arm64: dts: qcom: sm6350: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 09/11] arm64: dts: qcom: sm8350: " Konrad Dybcio
` (5 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 27f87835bc5595f5023319f77878a8ea4090a3f6..28e57ad885f4f64abbf429c337d45504ff2830ad 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4296,6 +4296,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
remoteproc_adsp: remoteproc@17300000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 09/11] arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (7 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 08/11] arm64: dts: qcom: sm8150: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 10/11] arm64: dts: qcom: sm8450: " Konrad Dybcio
` (4 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 37a2aba0d4cae0421c8ddc09d70373836dac8b33..3156aff90f16b32e8458bcc9a93e6fa6084c5a09 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3282,6 +3282,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
adsp: remoteproc@17300000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 10/11] arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (8 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 09/11] arm64: dts: qcom: sm8350: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-18 22:57 ` [PATCH RFC 11/11] arm64: dts: qcom: x1e80100: " Konrad Dybcio
` (3 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9bafb3b350ff627277514be83910b72a283c1935..a22112cb4bb5ba2f20e45f8136d9ec2d75dd7571 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4257,6 +4257,7 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
intc: interrupt-controller@17100000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH RFC 11/11] arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (9 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 10/11] arm64: dts: qcom: sm8450: " Konrad Dybcio
@ 2024-09-18 22:57 ` Konrad Dybcio
2024-09-19 7:00 ` [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Luca Weiss
` (2 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-18 22:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <quic_kdybcio@quicinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..d364d5ebdaaf6aa1935d42e49819b02e03e32fe9 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5738,6 +5738,8 @@ apps_smmu: iommu@15000000 {
#iommu-cells = <2>;
#global-interrupts = <1>;
+
+ dma-coherent;
};
intc: interrupt-controller@17000000 {
--
2.46.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (10 preceding siblings ...)
2024-09-18 22:57 ` [PATCH RFC 11/11] arm64: dts: qcom: x1e80100: " Konrad Dybcio
@ 2024-09-19 7:00 ` Luca Weiss
2024-09-19 10:07 ` Konrad Dybcio
2024-09-20 7:35 ` neil.armstrong
2024-10-07 14:25 ` Bjorn Andersson
13 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2024-09-19 7:00 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
> I only read back the SMMU config on X1E & 7280, but I have it on good
> authority that this concerns all RPMh SoCs. Sending as RFC just in case.
>
> Lacking coherency can hurt performance, but claiming coherency where it's
> absent would lead to a kaboom.
Hi Konrad!
You want people with the affected SoCs to test this I imagine?
Just boot it and see if it doesn't implode, or do you have any more
elaborate test plan for this?
Regards
Luca
>
> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
> ---
> Konrad Dybcio (11):
> arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
>
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++
> 11 files changed, 12 insertions(+), 1 deletion(-)
> ---
> base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5
> change-id: 20240919-topic-apps_smmu_coherent-070f38a2c207
>
> Best regards,
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs
2024-09-19 7:00 ` [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Luca Weiss
@ 2024-09-19 10:07 ` Konrad Dybcio
2024-09-19 18:48 ` Steev Klimaszewski
0 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2024-09-19 10:07 UTC (permalink / raw)
To: Luca Weiss, Konrad Dybcio, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 19.09.2024 9:00 AM, Luca Weiss wrote:
> On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
>> I only read back the SMMU config on X1E & 7280, but I have it on good
>> authority that this concerns all RPMh SoCs. Sending as RFC just in case.
>>
>> Lacking coherency can hurt performance, but claiming coherency where it's
>> absent would lead to a kaboom.
>
> Hi Konrad!
>
> You want people with the affected SoCs to test this I imagine?
Yeah, would be nice to confirm
>
> Just boot it and see if it doesn't implode, or do you have any more
> elaborate test plan for this?
No, booting should be enough of a test
Konrad
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs
2024-09-19 10:07 ` Konrad Dybcio
@ 2024-09-19 18:48 ` Steev Klimaszewski
0 siblings, 0 replies; 21+ messages in thread
From: Steev Klimaszewski @ 2024-09-19 18:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Luca Weiss, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers, Marijn Suijten,
linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
Hi Konrad,
On Thu, Sep 19, 2024 at 5:07 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> On 19.09.2024 9:00 AM, Luca Weiss wrote:
> > On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote:
> >> I only read back the SMMU config on X1E & 7280, but I have it on good
> >> authority that this concerns all RPMh SoCs. Sending as RFC just in case.
> >>
> >> Lacking coherency can hurt performance, but claiming coherency where it's
> >> absent would lead to a kaboom.
> >
> > Hi Konrad!
> >
> > You want people with the affected SoCs to test this I imagine?
>
> Yeah, would be nice to confirm
>
> >
> > Just boot it and see if it doesn't implode, or do you have any more
> > elaborate test plan for this?
>
> No, booting should be enough of a test
>
> Konrad
I have tested sc8280xp on the Thinkpad X13s. It still boots and
nothing seems to be more broken than usual (kidding, it seems to be
running exactly as it was before the patchset was applied.) I will
try to find the time to test sc8180x on a Flex 5G as well as the
sdm845 on the Lenovo Yoga C630, but I can't promise I'll find the
time.
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (11 preceding siblings ...)
2024-09-19 7:00 ` [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Luca Weiss
@ 2024-09-20 7:35 ` neil.armstrong
2024-10-07 14:25 ` Bjorn Andersson
13 siblings, 0 replies; 21+ messages in thread
From: neil.armstrong @ 2024-09-20 7:35 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, cros-qcom-dts-watchers
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 19/09/2024 00:57, Konrad Dybcio wrote:
> I only read back the SMMU config on X1E & 7280, but I have it on good
> authority that this concerns all RPMh SoCs. Sending as RFC just in case.
>
> Lacking coherency can hurt performance, but claiming coherency where it's
> absent would lead to a kaboom.
>
> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
> ---
> Konrad Dybcio (11):
> arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
> arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
>
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++
> 11 files changed, 12 insertions(+), 1 deletion(-)
> ---
> base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5
> change-id: 20240919-topic-apps_smmu_coherent-070f38a2c207
>
> Best regards,
Ran this serie in our CI, here's the pipeline: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba-tester/-/pipelines/104656
For some lab reasons, x1e80100 & onneplus-enchilada didn't boot, ignore them.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8150-hdk
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8350-hdk
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8450-hdk
Neil
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs
2024-09-18 22:57 [RFC PATCH 00/11] Affirm SMMU coherent pagetable walker capability on RPMh SoCs Konrad Dybcio
` (12 preceding siblings ...)
2024-09-20 7:35 ` neil.armstrong
@ 2024-10-07 14:25 ` Bjorn Andersson
13 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2024-10-07 14:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
cros-qcom-dts-watchers, Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On Thu, 19 Sep 2024 00:57:13 +0200, Konrad Dybcio wrote:
> I only read back the SMMU config on X1E & 7280, but I have it on good
> authority that this concerns all RPMh SoCs. Sending as RFC just in case.
>
> Lacking coherency can hurt performance, but claiming coherency where it's
> absent would lead to a kaboom.
>
>
> [...]
Applied, thanks!
[01/11] arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
commit: 7a52db70c8c5f4e2f6cf404b6cac10beae43f2bd
[02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
commit: 3d89c1984000171665d8091c7fdf20f9cf814786
[03/11] arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
commit: 57222f077bd05b6ef8c5b2998400122f3c202e51
[04/11] arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
commit: 2b73b83cb82aefb6c907ea91a9977641bbcae683
[05/11] arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
commit: e009473c5f5d62d4e0f093a3126cf98e319d8cd0
[06/11] arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
commit: 6b31a9744b8726c69bb0af290f8475a368a4b805
[07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
commit: 7abe72765d9f6a900a1c2b6c12b9dd70010a8b0b
[08/11] arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
commit: 05bd9923d15e8508cd0fa4f3d03437df1a9362aa
[09/11] arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
commit: 051ff563cb3d87c631c8997d9b3636a7b59a12b9
[10/11] arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
commit: c9ab6652769d331e39f7489241e8b3427f7e8608
[11/11] arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
commit: 5207d9c75f18db46ce42074f6585c7ca8e4aca75
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread