From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Christoph Hellwig <hch@lst.de>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Robin Murphy <robin.murphy@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Saravana Kannan <saravanak@google.com>,
Heikki Krogerus <heikki.krogerus@linux.intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:DMA MAPPING HELPERS"
<iommu@lists.linux-foundation.org>
Subject: Re: [PATCH 09/15] device core: Add ability to handle multiple dma offsets
Date: Wed, 20 May 2020 13:28:32 +0200 [thread overview]
Message-ID: <2aa6f276085319a5af7a96b3d7bdd0501641a7d7.camel@suse.de> (raw)
In-Reply-To: <20200519203419.12369-10-james.quinlan@broadcom.com>
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Hi Jim,
thanks for having a go at this! My two cents.
On Tue, 2020-05-19 at 16:34 -0400, Jim Quinlan wrote:
> The device variable 'dma_pfn_offset' is used to do a single
> linear map between cpu addrs and dma addrs. The variable
> 'dma_map' is added to struct device to point to an array
> of multiple offsets which is required for some devices.
>
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
[...]
> --- a/include/linux/device.h
> +++ b/include/linux/device.h
> @@ -493,6 +493,8 @@ struct dev_links_info {
> * @bus_dma_limit: Limit of an upstream bridge or bus which imposes a smaller
> * DMA limit than the device itself supports.
> * @dma_pfn_offset: offset of DMA memory range relatively of RAM
> + * @dma_map: Like dma_pfn_offset but used when there are multiple
> + * pfn offsets for multiple dma-ranges.
> * @dma_parms: A low level driver may set these to teach IOMMU code
> about
> * segment limitations.
> * @dma_pools: Dma pools (if dma'ble device).
> @@ -578,7 +580,12 @@ struct device {
> allocations such descriptors. */
> u64 bus_dma_limit; /* upstream dma constraint */
> unsigned long dma_pfn_offset;
> -
> +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> + const void *dma_offset_map; /* Like dma_pfn_offset, but for
> + * the unlikely case of multiple
> + * offsets. If non-null, dma_pfn_offset
> + * will be 0. */
I get a bad feeling about separating the DMA offset handling into two distinct
variables. Albeit generally frowned upon, there is a fair amount of trickery
around dev->dma_pfn_offset all over the kernel. usb_alloc_dev() comes to mind
for example. And this obviously doesn't play well with it. I feel a potential
solution to multiple DMA ranges should completely integrate with the current
device DMA handling code, without special cases, on top of that, be transparent
to the user.
In more concrete terms, I'd repackage dev->bus_dma_limit and
dev->dma_pfn_offset into a list/array of DMA range structures and adapt/create
the relevant getter/setter functions so as for DMA users not to have to worry
about the specifics of a device's DMA constraints. For example, instead of
editing dev->dma_pfn_offset, you'd be passing a DMA range structure to the
device core, and let it take the relevant decisions on how to handle it
internally (overwrite, add a new entry, merge them, etc...).
Easier said than done. :)
Regards,
Nicolas
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next prev parent reply other threads:[~2020-05-20 11:28 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 20:33 [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 03/15] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 08/15] of: Include a dev param in of_dma_get_range() Jim Quinlan
2020-05-19 20:34 ` [PATCH 09/15] device core: Add ability to handle multiple dma offsets Jim Quinlan
2020-05-20 5:43 ` Greg Kroah-Hartman
2020-05-20 13:50 ` Jim Quinlan
2020-05-20 14:03 ` Greg Kroah-Hartman
2020-05-20 11:28 ` Nicolas Saenz Julienne [this message]
2020-05-22 14:31 ` Jim Quinlan
2020-05-20 17:42 ` Christoph Hellwig
2020-05-20 18:26 ` Jim Quinlan
2020-05-20 22:36 ` Dan Williams
2020-05-21 8:19 ` Christoph Hellwig
2020-05-20 16:15 ` [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Bjorn Helgaas
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