From: Matthias Brugger <matthias.bgg@gmail.com>
To: Allen-KH Cheng <allen-kh.cheng@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: Project_Global_Chrome_Upstream_Group@mediatek.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
hsinyi@chromium.org
Subject: Re: [PATCH v5 1/6] arm64: dts: mediatek: mt8186: Add MTU3 nodes
Date: Mon, 29 May 2023 15:42:51 +0200 [thread overview]
Message-ID: <2ac28066-9798-79d7-5247-6af48ac95311@gmail.com> (raw)
In-Reply-To: <20230324021258.15863-2-allen-kh.cheng@mediatek.com>
On 24/03/2023 03:12, Allen-KH Cheng wrote:
> Add MTU3 nodes for MT8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index a0d3e1f731bd..178421fd8380 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -981,6 +981,40 @@
> status = "disabled";
> };
>
> + ssusb0: usb@11201000 {
> + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
> + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + clocks = <&topckgen CLK_TOP_USB_TOP>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
> + <&infracfg_ao CLK_INFRA_AO_ICUSB>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
> + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
> + phys = <&u2port0 PHY_TYPE_USB2>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usb_host0: usb@11200000 {
> + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + clocks = <&topckgen CLK_TOP_USB_TOP>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
> + <&infracfg_ao CLK_INFRA_AO_ICUSB>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
> + interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-wakeup = <&pericfg 0x420 2>;
> + wakeup-source;
> + status = "disabled";
> + };
> + };
> +
> mmc0: mmc@11230000 {
> compatible = "mediatek,mt8186-mmc",
> "mediatek,mt8183-mmc";
> @@ -1012,6 +1046,40 @@
> status = "disabled";
> };
>
> + ssusb1: usb@11281000 {
> + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
> + reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
> + <&clk26m>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
> + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usb_host1: usb@11280000 {
> + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
> + reg = <0 0x11280000 0 0x1000>;
> + reg-names = "mac";
> + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
> + <&clk26m>,
> + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
> + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,syscon-wakeup = <&pericfg 0x424 2>;
> + wakeup-source;
> + status = "disabled";
> + };
> + };
> +
> u3phy0: t-phy@11c80000 {
> compatible = "mediatek,mt8186-tphy",
> "mediatek,generic-tphy-v2";
next prev parent reply other threads:[~2023-05-29 13:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-24 2:12 [PATCH v5 0/6] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng
2023-03-24 2:12 ` [PATCH v5 1/6] arm64: dts: mediatek: mt8186: Add MTU3 nodes Allen-KH Cheng
2023-05-29 13:42 ` Matthias Brugger [this message]
2023-03-24 2:12 ` [PATCH v5 2/6] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Allen-KH Cheng
2023-03-24 2:12 ` [PATCH v5 3/6] arm64: dts: mediatek: mt8186: Add SPMI node Allen-KH Cheng
2023-03-24 2:12 ` [PATCH v5 4/6] arm64: dts: mediatek: mt8186: Add ADSP node Allen-KH Cheng
2023-03-24 2:12 ` [PATCH v5 5/6] arm64: dts: mediatek: mt8186: Add GCE node Allen-KH Cheng
2023-03-24 2:12 ` [PATCH v5 6/6] arm64: dts: mediatek: mt8186: Add display nodes Allen-KH Cheng
2023-04-14 1:27 ` [PATCH v5 0/6] Add and update some driver nodes for MT8186 SoC Allen-KH Cheng (程冠勳)
2023-05-29 13:46 ` Matthias Brugger
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