[PATCH v1 0/2] Enable CTCU device for QCS8300

[PATCH v1 0/2] Enable CTCU device for QCS8300

[Jie Gan]

Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
configurations as SA8775p platform.

Jie Gan (2):
  dt-bindings: arm: add CTCU device for QCS8300
  arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes

 .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
 2 files changed, 160 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v1 1/2] dt-bindings: arm: add CTCU device for QCS8300

[Jie Gan]

The CTCU device for QCS8300 shares the same configurations as SA8775p. Add
a fallback to enable the CTCU for QCS8300 to utilize the compitable of the
SA8775p.

Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
 .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml     | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index 843b52eaf872..7f3aa503da53 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -26,8 +26,13 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - qcom,sa8775p-ctcu
+    oneOf:
+      - items:
+          - enum:
+              - qcom,qcs8300-ctcu
+          - const: qcom,sa8775p-ctcu
+      - enum:
+          - qcom,sa8775p-ctcu
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes

[Jie Gan]

Add CTCU and ETR nodes in DT to enable expected functionalities.

Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 037cd366a09b..17a799e6f55e 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -2146,6 +2146,35 @@ lpass_ag_noc: interconnect@3c40000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		ctcu@4001000 {
+			compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
+			reg = <0x0 0x04001000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ctcu_in0: endpoint {
+						remote-endpoint = <&etr0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					ctcu_in1: endpoint {
+						remote-endpoint = <&etr1_out>;
+					};
+				};
+			};
+		};
+
 		stm@4002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x04002000 0x0 0x1000>,
@@ -2340,6 +2369,122 @@ qdss_funnel_out: endpoint {
 			};
 		};
 
+		replicator@4046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x04046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					qdss_rep_in: endpoint {
+						remote-endpoint = <&swao_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_rep_out0: endpoint {
+						remote-endpoint = <&etr_rep_in>;
+					};
+				};
+			};
+		};
+
+		tmc@4048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x04048000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04c0 0x00>;
+
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr0_in: endpoint {
+						remote-endpoint = <&etr_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr0_out: endpoint {
+						remote-endpoint = <&ctcu_in0>;
+					};
+				};
+			};
+		};
+
+		replicator@404e000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x0404e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etr_rep_in: endpoint {
+						remote-endpoint = <&qdss_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					etr_rep_out0: endpoint {
+						remote-endpoint = <&etr0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					etr_rep_out1: endpoint {
+						remote-endpoint = <&etr1_in>;
+					};
+				};
+			};
+		};
+
+		tmc@404f000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x0404f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04a0 0x40>;
+
+			arm,scatter-gather;
+			arm,buffer-size = <0x400000>;
+
+			in-ports {
+				port {
+					etr1_in: endpoint {
+						remote-endpoint = <&etr_rep_out1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr1_out: endpoint {
+						remote-endpoint = <&ctcu_in1>;
+					};
+				};
+			};
+		};
+
 		tpdm@4841000 {
 			compatible = "qcom,coresight-tpdm", "arm,primecell";
 			reg = <0x0 0x04841000 0x0 0x1000>;
@@ -2769,6 +2914,14 @@ out-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
+				port@0 {
+					reg = <0>;
+
+					swao_rep_out0: endpoint {
+						remote-endpoint = <&qdss_rep_in>;
+					};
+				};
+
 				port@1 {
 					reg = <1>;
 
-- 
2.34.1

Re: [PATCH v1 1/2] dt-bindings: arm: add CTCU device for QCS8300

[Krzysztof Kozlowski]

On Thu, Mar 27, 2025 at 10:49:42AM +0800, Jie Gan wrote:
> The CTCU device for QCS8300 shares the same configurations as SA8775p. Add
> a fallback to enable the CTCU for QCS8300 to utilize the compitable of the
> SA8775p.
> 
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml     | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v1 2/2] arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes

[Konrad Dybcio]

On 3/27/25 3:49 AM, Jie Gan wrote:
> Add CTCU and ETR nodes in DT to enable expected functionalities.
> 
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v1 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 3/27/2025 10:49 AM, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
> 

Gentle ping for the series.

dt-binding patch has been reviewed by Krzysztof.
dts patch has been acked by Konrad.

Thanks,
Jie

> Jie Gan (2):
>    dt-bindings: arm: add CTCU device for QCS8300
>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
> 
>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>   2 files changed, 160 insertions(+), 2 deletions(-)
> 

Re: [PATCH v1 0/2] Enable CTCU device for QCS8300

[Bjorn Andersson]

On Wed, May 14, 2025 at 04:00:12PM +0800, Jie Gan wrote:
> 
> 
> On 3/27/2025 10:49 AM, Jie Gan wrote:
> > Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> > the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> > configurations as SA8775p platform.
> > 
> 
> Gentle ping for the series.
> 
> dt-binding patch has been reviewed by Krzysztof.
> dts patch has been acked by Konrad.
> 

You don't seem to have the Coresight maintainers among the recipients of
the binding patch, so that's probably why it hasn't been merged yet -
and I can't merge the DTS change until the binding is accepted.

Please apply Krzysztof's R-b and send the binding alone to Coresight
maintainers, once they have accepted the binding please resubmit the dts
change and I'd be happy to merge it. (v2 sounds good on both)

PS. Please see go/upstream on how to adopt b4; "b4 prep --auto-to-cc"
would have saved you from this mistake.

Regards,
Bjorn

> Thanks,
> Jie
> 
> > Jie Gan (2):
> >    dt-bindings: arm: add CTCU device for QCS8300
> >    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
> > 
> >   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
> >   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
> >   2 files changed, 160 insertions(+), 2 deletions(-)
> > 
> 

Re: [PATCH v1 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 6/18/2025 10:50 AM, Bjorn Andersson wrote:
> On Wed, May 14, 2025 at 04:00:12PM +0800, Jie Gan wrote:
>>
>>
>> On 3/27/2025 10:49 AM, Jie Gan wrote:
>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
>>> configurations as SA8775p platform.
>>>
>>
>> Gentle ping for the series.
>>
>> dt-binding patch has been reviewed by Krzysztof.
>> dts patch has been acked by Konrad.
>>
> 
> You don't seem to have the Coresight maintainers among the recipients of
> the binding patch, so that's probably why it hasn't been merged yet -
> and I can't merge the DTS change until the binding is accepted.
> 
> Please apply Krzysztof's R-b and send the binding alone to Coresight
> maintainers, once they have accepted the binding please resubmit the dts
> change and I'd be happy to merge it. (v2 sounds good on both)
> 
> PS. Please see go/upstream on how to adopt b4; "b4 prep --auto-to-cc"
> would have saved you from this mistake.
> 

Thanks for the information.

Will re-send the patch series.

Thanks,
Jie

> Regards,
> Bjorn
> 
>> Thanks,
>> Jie
>>
>>> Jie Gan (2):
>>>     dt-bindings: arm: add CTCU device for QCS8300
>>>     arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>>
>>>    .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>>    2 files changed, 160 insertions(+), 2 deletions(-)
>>>
>>