From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F6D2C4332F for ; Wed, 16 Nov 2022 12:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233638AbiKPM6p (ORCPT ); Wed, 16 Nov 2022 07:58:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233496AbiKPM6m (ORCPT ); Wed, 16 Nov 2022 07:58:42 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B919C659D for ; Wed, 16 Nov 2022 04:58:40 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id kt23so43878339ejc.7 for ; Wed, 16 Nov 2022 04:58:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=nDvwwXEV44aTmmIoKPH7bc6LqlZ8E4Ob4p52TWVGvr4=; b=cekHUYpnORylDQCbKrdKPLGkpBFRddBfMwumZYLprtEW+p5C2UDnouejqfjrWJzI4J 8OhYuUwZdDjveaJCpvi4j6DWMB+mJpJleUVnpDYxrs7maHuyry3aSib5+qOmaXyhXA/n nK5vSoTK719b4vBpZ5r30dGWC8GtvYGZd3dMtsrL+D993WOv8adOqln8zPKUBqclhdMb ZCeXycgrStly31vJKY4Gx1CcZ85xGMPfETqaRZH/fqXXUST7pOXM2/r4BVJRiLfeECAV qkNbie+sL3F4spPeYk+5l8oRjv8RzOcmibjoMAcZoNeO69YRhujrnBKd+QuqMiTozStj iWGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nDvwwXEV44aTmmIoKPH7bc6LqlZ8E4Ob4p52TWVGvr4=; b=QW3ge9KddOKJnAZqz73FfTAarMh0WAGw0v0itWd5LgePC7fMvPokzeJC4qkuM2v30Q Hc+WS5/Mj5FeV8Qm6MHIjKG1WscfXXBj2GMf3Q+b/ue38q3GBQ/w9jHLH5O+ScvkcztV 9UgUwNi6y6BS5lY26C68ZwSAQQXwqj0yB1VJoODBoZhVIVpI40QuYHGezTl2SIBwLX9q IvZgQq30+xkKFCPUv3dUMOSa9jhd6wiuf26JGIitSqTZAkCtlgB7pEHYGEKn/myyvYe1 sbQdzURsJcn8GBUaSMYAOGJo5z+av2LgVKY02QaZ+dul+pOY9lzi0n0wFS2J6UvBur31 Rv6w== X-Gm-Message-State: ANoB5pm93xyBN7mcSrKEPb/DBBdK8ksD1ne50g/weNJRLXqptf0AMRLu EN1ZbAD85d46ZatKF+wDU5JTQQ== X-Google-Smtp-Source: AA0mqf56KN02I0QAyi1K7BJ8yHmTXAi5FUUAmYTDqbHwTr24Kj7vjxOkDm2xehoN6rUfBRJ6JRfEHg== X-Received: by 2002:a17:906:1d08:b0:7a9:ecc1:2bd2 with SMTP id n8-20020a1709061d0800b007a9ecc12bd2mr17517688ejh.545.1668603519342; Wed, 16 Nov 2022 04:58:39 -0800 (PST) Received: from [192.168.31.208] ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id we10-20020a170907234a00b00782fbb7f5f7sm6844407ejb.113.2022.11.16.04.58.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Nov 2022 04:58:38 -0800 (PST) Message-ID: <2b5f65f9-99d0-4ce6-da18-c1d9c8898d70@linaro.org> Date: Wed, 16 Nov 2022 13:58:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes To: Abel Vesa , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20221116125112.2788318-1-abel.vesa@linaro.org> <20221116125112.2788318-2-abel.vesa@linaro.org> From: Konrad Dybcio In-Reply-To: <20221116125112.2788318-2-abel.vesa@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 16/11/2022 13:51, Abel Vesa wrote: > Add UFS host controller and PHY nodes. > > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 76 ++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 07ba709ca35f..27ce382cb594 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1372,6 +1372,82 @@ mmss_noc: interconnect@1780000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + ufs_mem_phy: phy@1d80000 { > + compatible = "qcom,sm8550-qmp-ufs-phy"; > + reg = <0x0 0x01d80000 0x0 0x200>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; These three can go at the bottom. > + clock-names = "ref", "qref"; > + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&tcsr TCSR_UFS_CLKREF_EN>; > + > + power-domains = <&gcc UFS_MEM_PHY_GDSC>; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + status = "disabled"; > + > + ufs_mem_phy_lanes: phy@1d80400 { > + reg = <0x0 0x01d81000 0x0 0x134>, > + <0x0 0x01d81200 0x0 0x3d8>, > + <0x0 0x01d80400 0x0 0x258>, > + <0x0 0x01d81800 0x0 0x134>, > + <0x0 0x01d81a00 0x0 0x3d8>; > + #phy-cells = <0>; > + }; > + }; > + > + ufs_mem_hc: ufshc@1d84000 { > + compatible = "qcom,sm8550-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = ; > + phys = <&ufs_mem_phy_lanes>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc UFS_PHY_GDSC>; > + > + iommus = <&apps_smmu 0x60 0x0>; > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; > + > + interconnect-names = "ufs-ddr", "cpu-ufs"; > + clock-names = Why break the line before adding any entries? Konrad > + "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + clocks = > + <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_LN_BB_CLK3>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + freq-table-hz = > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <100000000 403000000>, > + <0 0>, > + <0 0>, > + <0 0>; > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>;