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Wed, 13 May 2026 11:55:42 -0700 (PDT) X-Received: by 2002:a05:6a00:330a:b0:834:e882:3280 with SMTP id d2e1a72fcca58-83f05bf518emr4410478b3a.31.1778698541428; Wed, 13 May 2026 11:55:41 -0700 (PDT) Received: from [192.168.0.17] ([49.205.251.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19778c87sm244376b3a.19.2026.05.13.11.55.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 May 2026 11:55:40 -0700 (PDT) Message-ID: <2b8e84ed-1f01-3936-0fd9-b5249ba5832c@oss.qualcomm.com> Date: Thu, 14 May 2026 00:25:29 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH v5 10/14] media: iris: Add power sequence for Glymur To: Dmitry Baryshkov Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Joerg Roedel , Will Deacon , Robin Murphy , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Jorge Ramirez-Ortiz , Del Regno , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, Krzysztof Kozlowski , devicetree@vger.kernel.org References: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> <20260509-glymur-v5-10-7fbb340c5dbd@oss.qualcomm.com> <67157e35-8c39-b06b-eb93-602930168f4b@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE4NiBTYWx0ZWRfX4gXoLrWAODEg E59YngNR+qbUkAQycIvYWlK5prsxsAA7ofPP9mvmcwFj02s6PL+TN7rkPl2WYu/mQPWfnv+EfZh HpdDMn0Ik432KPmXDRP3GjzKFMJJi5zanXb3q197aAqXUvtmyD+uxZKxfuzxI5PEbbWuMIXOhJO cPiMX7SXNVlU6OiBX8AK6wu60p+Wv9UGYgsfTvsz7dPRlBghISOKRUjrOIKcDYVxx6YElucXEan E0lfHC3cvCcyC5yTA1B4Uwq18r1mZmDOEBgQRsmMhPwy9JA471xPrk1DGai5PffRvWNghgPJS7v jTYbL/JyvcrudQ4ECyC0TdwFvoA+rUIhS2NlzWRNQgrt8+b88k2EgMpVI3hQQ/NygZ4BHBTr4z9 +Yd99lFHn3iFAS2B25J6Q6dNgoy7KjjdD2cO5RpgkoSuzNQ2lZHP+hKAY5dYLyYHI2rIMC5dg+V ERMI/V/spv194ngvtNw== X-Authority-Analysis: v=2.4 cv=XqXK/1F9 c=1 sm=1 tr=0 ts=6a04c92f cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=UdqKVphAFhxg2bWZaUV5ew==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=Aj1sxsqqlx8X5QhbYpsA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: pEMuLF2v5r0G5BW-wAndWeM2TowFonDG X-Proofpoint-GUID: pEMuLF2v5r0G5BW-wAndWeM2TowFonDG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_02,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130186 On 5/13/2026 7:19 PM, Dmitry Baryshkov wrote: > On Mon, May 11, 2026 at 09:42:01PM +0530, Vishnu Reddy wrote: >> On 5/9/2026 2:24 AM, Dmitry Baryshkov wrote: >>> On Sat, May 09, 2026 at 12:29:59AM +0530, Vishnu Reddy wrote: >>>> Glymur has a secondary video codec core (vcodec1), equivalent to the >>>> primary core (vcodec0), but with independent power domains, clocks, >>>> and reset lines. Reuse the existing code wherever possible and add >>>> power sequence for vcodec1. >>>> >>>> Reviewed-by: Vikash Garodia >>>> Signed-off-by: Vishnu Reddy >>>> --- >>>> .../platform/qcom/iris/iris_platform_common.h | 4 + >>>> drivers/media/platform/qcom/iris/iris_vpu3x.c | 141 ++++++++++++++++++++- >>>> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + >>>> .../platform/qcom/iris/iris_vpu_register_defines.h | 10 ++ >>>> 4 files changed, 154 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h >>>> index 7d59e6364e9d..8995136ad29e 100644 >>>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h >>>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h >>>> @@ -61,6 +61,9 @@ enum platform_clk_type { >>>> IRIS_VPP0_HW_CLK, >>>> IRIS_VPP1_HW_CLK, >>>> IRIS_APV_HW_CLK, >>>> + IRIS_AXI_VCODEC1_CLK, >>>> + IRIS_VCODEC1_CLK, >>>> + IRIS_VCODEC1_FREERUN_CLK, >>> I think I have asked the same question while reviewing some other code. >>> When seeing such enums my expectation would be that the set of clocks is >>> more or less generic, while the platform specifics should be >>> encapsulated in platform-specific code. Instead these lists keep on >>> growing to accomodate platform details. >>> >>> Can we stop that tradition? Adding a peculiarity of the platform should >>> not require touching of the generic code. >>> >>>> }; >>>> >>>> struct platform_clk_data { >>>> @@ -210,6 +213,7 @@ enum platform_pm_domain_type { >>>> IRIS_VPP0_HW_POWER_DOMAIN, >>>> IRIS_VPP1_HW_POWER_DOMAIN, >>>> IRIS_APV_HW_POWER_DOMAIN, >>>> + IRIS_VCODEC1_POWER_DOMAIN, >>>> }; >>>> >>>> struct platform_pd_data { >>>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>>> index 13fbb21c2182..ff90c375e805 100644 >>>> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c >>>> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>>> @@ -22,9 +22,19 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) >>>> u32 value, pwr_status; >>>> >>>> value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >>>> - pwr_status = value & BIT(1); >>>> + pwr_status = value & VCODEC0_POWER_STATUS; >>>> >>>> - return pwr_status ? false : true; >>>> + return !pwr_status; >>>> +} >>>> + >>>> +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) >>>> +{ >>>> + u32 value, pwr_status; >>>> + >>>> + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); >>>> + pwr_status = value & VCODEC1_POWER_STATUS; >>>> + >>>> + return !pwr_status; >>> Add core as an argument to the function instead of c&p'ing it. >> Ack, will pass the vcodecx_power_status bit to this function. > u32 core, please. core is already used as a struct iris_core * pointer in this function. I'll use a different name like pwr_status_bit for the u32 argument instead. >>>> } >>>> >>>> static void iris_vpu3_power_off_hardware(struct iris_core *core) >>>> @@ -254,6 +264,124 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) >>>> iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); >>>> } >>>> >>>> +static int iris_vpu36_power_on_hw1(struct iris_core *core) >>> Hmmm... And if 3.7 gets 4 cores, will we have 4 copies of the function? >> As of now, none of the near upcoming targets introduce a significantly higher >> number of cores. If that changes in the future, we can revisit and optimize it >> then. > Okay.... >